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  Back to ADS 2015.01 Release Notes 

Key Features

Layout Features

  • From ADS 2015.01, trace is a refined object that regenerates itself when one of its elements is edited or when the connected objects are moved.
    ADS 2015.01 traces overcomes the limitations of paths and ADS 2014.01 traces, and supports:
    • endcaps and improved corners.
    • maintaining entry angle into the pins when the trace is edited or when the connected components are moved.
    • editing the entire trace as a single object.
    • editing individual elements of a trace.
    • auto-resizing vias when segments of the trace are resized.
    • auto-regeneration to optimize number of vertices in the trace while editing.
    • auto complete trace routing with 90 degree angle entry mode.
    • polymorphic trace simulation with different levels of accuracy without modifying the layout or schematic view.

For information on trace differences between ADS 2014.01 and ADS 2015.01, see Trace Differences.
For information on traces, see Working with Traces.

  • Layout and schematic toolbars have been reconfigured to various smaller toolbars. This enables you to personalize ADS to your needs. For information on reconfigured toolbars, see Layout and Schematic Toolbars.
  • New and improved Layout and schematic hotkeys. There are now single-key hotkeys for various common operations such as M for move. For information on list of hotkeys, see Layout Hotkeys.
  • From ADS 2015.01, ADS layout can operate in any of the following connectivity modes.

    • WYSIWYG Mode: Break and join nets automatically
    • WYSIWYG Mode: Create physical wires
    • Net Based: Don't break or join nets automatically

    WYSIWYG Mode is the default connectivity mode for all the design flows (such as RF/Microwave, Electrothermal, Digital Signal Processing, Interoperability (OpenAccess), GoldenGate in ADS, PDK Development) except HSD. The default connectivity mode for HSD design flow is Net Based. For more information, see Connectivity Modes.


  • ADS 2015.01 requires: a) version 2014.07 of the EEsof EDA licensing software, b) version 3.2 codewords to run, and c) the licensing server software, lmgrd and agileesofd, to be upgraded to at least the same versions as what are included in EEsof EDA Licensing software 2014.07. ADS will not start if any of these requirements is not met. Refer to the License Codeword Version Compatibility Table.
  • In the EEsof EDA License Tools version 2014.07, licensing vendor daemon (agileesofd) is upgraded to sync up with FlexNet FNP version of FLEX license manager (lmgrd). ADS installer for the Windows platform will automatically set up these two new license server daemons by default for the local node-locked license users; for Linux, you need to follow the Linux/Solaris Licensing Setup instruction to complete the licensing configuration process. For more details, refer to Licensing (For Administrators).


Silicon RFIC Interoperability

Silicon RFIC Interoperability allows ADS to edit and simulate designs created in Cadence Design System's Virtuoso software and vice-versa. This feature was introduced as beta version for ADS 2014.01 as it depends on the availability of an enabled Virtuoso baseline PDK.

The following list are the specific features that are added as part of the Silicon RFIC Interoperability in this release:

For more details, see IC Interoperability.

Signal Integrity and Power Integrity for High-Speed Digital Design

DDR Bus Simulator

DDR Bus Simulator is a new product for this release. It calculates DQ and DQS eye probability density distributions and bit-error-rate (BER) in memory interfaces by using ultra-fast statistical simulations, achieving results that would be impossible with a conventional, SPICE-like transient simulation. It enables DDR designers to efficiently yet accurately simulate and optimize channel performance and to verify timing and voltage margins against the DDR4 Rx mask specification at extremely low BER level (e.g. the 1E-16 contour specified by JEDEC). This new simulator features:

  • Rigorous DQ and DQS eye calculations to arbitrarily low BER levels
  • Built-in driver de-emphasis and receiver continuous-time-linear-equalizer models
  • Mix-and-match between built-in, IBIS and circuit models of driver and receiver
  • Account for crosstalk between signal lines
  • Capture asymmetry between rise and fall edges
  • Comprehensive margin measurements versus JEDEC DDR4 Rx mask at target BER
  • Batch simulation for design space exploration and design of experiments

The simulator achieves this by use of statistical simulation, meaning no lengthy and time-consuming bit pattern is needed. Instead, it constructs the eye diagram from the transmitter, channel, and receiver impulse responses, and from the stochastic properties of a conceptually infinite non-repeating bit pattern.

For details, see DDR Simulation.

Channel Simulator

The following capabilities are new:

  • Significant speedup of ChannelSim bit-by-bit mode for ADS flow using ADS components
  • Performance of ChannelSim with multiple eye probes is improved by multithreading eye probe computation.

IBIS Specification Support

The following capabilities are new:

  • Improved the ability to handle the overclocked IBIS models, especially the power-aware IBIS models, which include a delay between the pre-driver circuit and the driver. For more information, refer to IBIS model BIRD 168.1.

Controlled Impedance Line Designer

The following capabilities are new:

  • New optimization mode that finds the optimal parameter value targeting a specific impedance goal.
  • New coplanar line types. Support for single-ended and edge-coupled coplanar waveguide lines was added.
  • New trapezoidal conductors. Conductors with a trapezoidal cross-section can be modeled now.

Post-layout Artwork Import

  • ADS Layout has been enhanced so that even very large designs can be imported and prepared for EM simulation. For example, ODB++ import, navigation, repainting, cookie cutting, and port setup are now much faster for large designs. This capability is particularly useful in cases where post-layout artwork is not created in ADS Layout, but in an enterprise PCB tool such as high-speed digital design using Xpedition from Mentor Graphics.

EM Simulation

Common Features to Momentum and FEM

  • Through-silicon vias can be defined in the Substrate Editor and be modeled with the Momentum or FEM simulators. 
  • New EM Setup Preprocessor option to scale the layout before it is sent to the Momentum or FEM simulator. This facilitates migration of a design from a full node to a shrink or half-node process. The performance of a passive device in the half-node process can be verified without the need to change your full node design database. For example, in case of a 45nm full-node and 40nm half-node, set a scale factor of 0.88889.
  • New EM Model menu picks under Tools to create a dataset and to open Data Display for a selected data item in the EM Model database.
  • New V_Probe component that can be placed in a Circuit/EM co-simulated layout to probe the voltage at a specific location in the layout partition that is simulated by EM.
  • The auto-generation of a black-box (dual or quad) symbol has been enhanced with 
    • New option to create one symbol pin per EM port in the layout. An EM Model netlist option is available to produce a netlist that matches with such symbol.
    • New option to include the net name in addition to the pin name in the symbol pin label
  • The EM Excitation Addon supports transient simulation. The time domain voltages are converted to the frequency domain to allow post-processing at the available frequencies.
  • New EM > Tools menus that support creating pins from selected shapes, adding selected shapes to pins, or dissociate selected shapes from pins


  • New net-based simulation options.  The physical model and mesh options can be specified per net. For example, the 3D-Distributed model can be specified for the conductors and vias on a critical signal net, while the Sheet and Lumped model are selected for respectively the conductors and vias on the power/ground nets.
  • New Sheet model for thick conductors. This is the recommended setting for power/ground planes or metal shields when a thick conductor is mapped in the substrate. The Sheet model for a thick conductor leads to the same number of unknowns as a sheet conductor in the substrate, but it is more accurate because it takes the metal thickness into account in mutual coupling computations with other parts of the circuit.
  • New solver option controls the compression level of the Direct Compressed solver. For more information, see Defining Solver Settings.


  • CPW ports

Circuit Simulation


2015.01 updates to the Verilog-A/MS 2.90.320 release from Tiburon Design Automation. Users distributing Verilog-A models in compiled form should review the 2015.01 documentation “Protecting IP by distributing Verilog-A in compiled form”, Verilog-A in ADS Design Kits. Compiled modules from 2014.01 will not simulate in 2015.01. Also in 2015.01 a single shared library per compiled library is now created; 2014.01 used per-module object files. The simulation time link required in 2014.01 is also avoided for compiled models. More detailed documentation on building compiled modules has been added to the system.


Passive - RF Bondwires

  • For all new bondwire design, we recommend to use the EBOND components from the standard "ads_bondwires" library.
  • New "ads_bondwires:EBOND_Shape" component with bondwire shape profile editor.
  • New Bondwire Utility Tools AEL addon. This addon bundles utilities in support of working with the EBOND components.
    Previously, the design kit mechanism was used for distribution of both the deprecated PBOND components and the bondwire utility tools.
    Remove the BondwireUtility_DKit design kit from the libraries used by the workspace (ADS Main Window > Design Kit > Manage Libraries...).
    The PBOND_lib components are still available through a PBOND design kit for existing designs that use the PBOND components. This design kit can be found under $HPEESOF_DIR/ial/design_kit/ Install the design kit to make use of these components.


Instance Name Mapping

  • New option enabled in the Options tab.
  • Equivalent components are determined by component type, pin connections and instance name.
  • Supported for:
    • Device Recognition
    • Component-Based LVS Analysis
  • Instance name mapping is a more rigorous check.
    • All instance names must match (including design hierarchy instances).
    • All Term names must match (previously, LVS would look only at Term number).
  • Benefits:
    • Removes false parameter mismatches due to ambiguity in the circuit topology.
    • Helps maintain consistent instance names between schematic and layout which supports real-time feedback on missing connections.
      • Missing connections will be displayed with dashed lines.
        • To see this, move a component in layout
        • Use [Shift]-drag to break connections
        • Dashed lines will display showing that the pins are connected in schematic and not in layout
    • Ease of troubleshooting errors in large designs
      • Enable the following options to get the most information for troubleshooting
        • Component-based LVS 
        • Hierarchy Check: All levels - similar hierarchy
      • Methodology
        • Run LVS from the top design using similar hierarchy check
        • LVS identifies the problem down inside the design hierarchy
        • Browse to the error in the LVS report
        • LVS will display the subdesign
        • Fix the error and check for a clean LVS at this level
        • Run LVS from the top-level design
        • Using this methodology you will quickly converge on a clean design

Parameter Value Mapping

  • New option enabled in the Options tab.
  • Equivalent components are determined by component type, pin connections and parameter values.
  • Supported for:
    • Device Recognition
    • Component-Based LVS Analysis
  • Parameter value mapping is a more rigorous check.
    • All parameter values must match in order for the LVS analysis to complete.
    • Supports designs that do not have similar design hierarchy.


New DRC rules commands

  • Net-based qualifiers support in DRC Clearance rules to perform checks based on the same net and diff net properties.

  • A Poly Touch Count function to select the touching polygons for a given constraint.

  • Support of Poly Area Density for work (derived) layers in DRC rule decks.


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