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VCO_DivideByN (VCO Divide By N)


Available in ADS and RFDE







Frequency deviation from F0 (function of _v1)


10 MHz × _v1


VCO center frequency




Nominal divide number (with dN=0)




Output resistance of VCO




Output power into Rout load




Transit time delay added to input tuning voltage



Pin Connections

tune connects to a tuning voltage.
dN connects to ground (dN=0) or a voltage source such as V_DC.
dN takes the value of nodal voltage and N+dN becomes the divide ratio.
vcon is the divided-by-(N+dN) output.
freq outputs the undivided frequency values from pin VCO. This pin can be left open.
VCO is the undivided VCO output. This pin can be left open if an undivided VCO is not used.

  1. This VCO model allows for the definition of an arbitrary, nonlinear frequency tuning characteristic. In addition, it incorporates a behavioral, divide by N model. Incorporating the divider into the same model permits its use in phase-lock loop simulations where the envelope bandwidth, as determined by the analysis time-step, does not have to include the entire tuning range of the VCO, but only the frequency range of the divided output. In these cases, the phase and frequency information of the VCO's main output may be aliased because of the large time-step. But, if just the divided output is being used, the loop simulations will still be valid and can simulate faster due to the large time-step.
    As the time-step is decreased, or the range of the VCO is reduced, such that it remains within the envelope bandwidth, then both the main VCO and the divided VCO output are valid. As with the standard VCO model, the phase of this model's outputs are also clamped when time=0 so this model only functions as a VCO in the time-domain analysis modes, including circuit envelope and transient simulations.
  2. The frequency of the VCO is determined by the F0 value plus the VCO_Freq value. The VCO_Freq value may be an arbitrary expression using _v1, which is a pre-defined variable representing the input tuning voltage. The frequency is determined inside the model by determining the present value of _v1 (the input voltage), evaluating the VCO_Freq expression and adding this to the F0 value. This frequency is output, as an ideal voltage source scaled to 1V per GHz, on the freq output pin.
  3. In circuit envelope simulation, the carrier frequency envelope associated with the main VCO frequency is determined by the F0 value. If there is no analysis harmonic frequency close enough to F0, then a warning is generated and the main output is zero. The carrier frequency envelope associated with the divided VCO frequency is determined by F0/N. Again, if no analysis harmonic frequency is close enough, then a warning is generated and this output is also set to zero.
  4. The divide number is determined by adding the N parameter and the dN baseband input voltage. The divide number can change during the simulation. By properly driving the dN input, fractional frequency division can be simulated. To simulate all the dynamics of a fractional divider, the simulation time-step must be small enough to properly digitize the varying divide- or pulse-swallowing rate. Alternatively, either the N value or the dN input can be set to fractional values to obtain a steady-state, fractional division that would not include the switching dynamics and spurs. In circuit envelope simulation, the divided VCO frequency must remain within its initial envelope bandwidth for all combinations of VCO frequencies and divide numbers. It will not automatically jump from one envelope carrier frequency to another. In transient simulation, because everything is treated as baseband signals, the only constraint is that the time-step must be small enough to cover the maximum frequency.
  5. Both the main VCO output and the divided output have an output resistance set by the Rout parameter. The main VCO output will deliver the specified Power into a Rout load. The divided output will also deliver this amount of power if it is not a baseband output. If it is a baseband output, then the divided output is a sawtooth waveform, whose open circuit voltage represents the instantaneous phase, in radians, of the divided signal. In transient simulation, then, this divided output is always a sawtooth. In circuit envelope, it is a sawtooth if F0/N is within the baseband envelope (it is less than 0.5/timestep). If F0/N is closer to one of the analysis carrier frequencies, then the output is a complex sinusoid with the same amplitude as the main VCO output.
  6. A Delay parameter value can also be specified for this VCO model. This puts an additional transit delay between the input tuning voltage and the actual change in the output frequency. A delay of at least one timestep does sometimes result in slightly faster simulation speeds, and can be used to model the time delay inherent in any real VCO.
  7. Care should be taken when using the VCO in baseband mode. If F0+VCO_Freq value goes negative, the model will generate a negative frequency, which may give unexpected results. If this is a problem, the VCO_Freq expression could include a limiting operator to prevent this.
  8. Example with Linear Tuning Characteristics shows an example application; simulation results are shown in Simulation Results. The tuning characteristic is linear in this case and is simply 1 MHz per volt. The nominally divided output frequency is 100MHz/55=1.81818 MHz, so this output can be a baseband output, given the 0.1 µ timestep. The divide number changes from 95 to 55 halfway through the simulation. (Note that while the divided VCO output may not appear to be a regular, uniform, amplitude sawtooth waveform, it does accurately represent the divided signal's phase.)
  9. The frequency can be determined by calculating the phase slope; by using linear interpolation, the baseband phase frequency detectors can accurately determine threshold crossings.

Example with Linear Tuning Characteristics

Simulation Results
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