Page tree
Skip to end of metadata
Go to start of metadata



PhaseFreqDet2 (Frequency Detector, Baseband)

Symbol

Available in ADS and RFDE

Parameters

Name

Description

Units

Default

Vhigh

High-state output voltage

V

5

Vlow

Low-state output voltage

V

0

DeadTime

Dead zone pulse width

psec

0

Jitter

Input time jitter

psec

0

Notes/Equations
  1. This baseband phase-frequency demodulator is used in transient or circuit envelope simulation. It models the digital behavior of common D flip-flop type phase-frequency detectors often used in phase-locked loops. The four outputs are ideal, zero impedance voltage sources. The two inputs have infinite impedance, and only the baseband portion of the two input voltages are used to determine threshold-crossing timing.
  2. The following FDD modeling equations illustrate how the shape of the four outputs relate to the input phase difference.
    The phase difference between the input on port 1 and port 2 is calculated as
    ns=_phase_freq(1,2), and the quantities n1= (Vhigh-Vlow) x real(ns) and
    n2= (Vhigh-Vlow) x imag(ns) are introduced.
    Outputs on ports 3-6 are then
    port 3: Q1=Vlow + n1
    port 4: Q2_bar = Vhigh - n2
    port 5: Q1_bar = Vhigh - n1 (only PhaseFreqDet2, not PhaseFreqDet)
    port 6: Q2 = Vlow + n2 (only PhaseFreqDet2, not PhaseFreqDet)
    with the following trigger events:
    Trig[1] = _xcross (1,0.5,1)
    Trig[2] = _xcross (3,0.5,1)
    For details about these functions, refer to the FDD device documentation in the Circuit Components Nonlinear Devices manual.
    Note that you can push into the component to see the implementation of the component.
  3. As opposed to the tuned phase-frequency detector model, this model's output includes reference clock feed-through effects.

    Note The output of this model is a pulse train whose average value is proportional to the input phase difference, and may contain significant signal energy at the reference clock rate, and at clock harmonics. Typically, these must be filtered out before driving a VCO in a PLL application. The tuned phase-frequency detector output signal includes instantaneous phase difference information only (it does not contain reference frequency or harmonic content).

    However, the penalty for this is that the timestep must be less than one-half the reference period, and typically less than one-tenth the period. To avoid the large amount of time jitter and phase noise that would normally be introduced by sampling at even these rates, the four digital outputs are also amplitude modulated to reflect the portion of a simulation timestep where the actual outputs would be high or low. For example, if based on the threshold-crossing timing (the pulse width should be 10 nsec, but the simulation timestep is 1µ), then the output amplitude for that timestep would only be 1% of the Vhigh level. While this will not properly model all the higher harmonics of the reference feed-through, it does accurately model both the dc term and the first few harmonics, and the corresponding reference sidebands of the VCO. As the analysis timestep is further reduced, the behavior becomes more truly digital in nature and more harmonics are effectively being simulated at the cost of slower simulations.
  4. The trigger times for both inputs is determined by detecting when the baseband voltage rises through the 0.5V threshold. Linear interpolation is used to get much finer time resolution than the analysis timestep. To further reduce excessive sampling jitter, inputs to this detector can be sawtooth waveforms. While the detector will work reasonably well with sinusoidal inputs, given a small enough timestep, the timing jitter can be eliminated if the interpolation is done on the positive slope of a sawtooth waveform. This is the reason why the divide-by-N models output a sawtooth waveform when they operate in the baseband mode. Square wave-inputs should generally be avoided, because this will usually introduce significant timing jitter and phase noise into the simulation.
  5. DeadTime specifies the period of time centered around the 0 phase output during which no output is generated from either the high or the low charge pump. Outside of this period, the output returns to the ideal pulse widths and amplitudes determined by the trigger crossings of the inputs and the charge pump currents.
  6. The Jitter value defines the RMS time jitter associated with a trigger crossing on either input. The distribution is Gaussian and the noise spectrum is assumed flat out to the reference sampling frequency.
  7. Other effects, such as asymmetry between the four different outputs, can be incorporated by changing the external components. One application of detector shows one application of this detector and Resultant output waveforms of detector the resultant output waveforms.

One application of detector

Resultant output waveforms of detector
  • No labels