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PhaseFreqDet (Frequency Detector, Baseband)

Symbol

Available in ADS

Parameters

Name

Description

Units

Default

Vhigh

High-state output voltage

 

 

Vlow

Low-state output voltage

 

 

Notes/Equations
  1. PhaseFreqDet is not selectable from the component palette or component library browser; to place this component, type its exact name into the Component History box above the drawing area, then move your cursor to the drawing area.
  2. This baseband phase-frequency demodulator is used in transient or circuit envelope simulation. It models the digital behavior of common D flip-flop type phase-frequency detectors often used in phase-locked loops. The two outputs are ideal, zero impedance voltage sources; to model a pulsed current-source output, two VDCS-dependent sources must be added to the output of this model. The two inputs have infinite impedance, and only the baseband portion of the two input voltages are used to determine threshold-crossing timing.
  3. As opposed to the tuned phase-frequency detector model, this model's output includes the effect of reference clock feed-through.

    Note The output of this model is a pulse train whose average value is proportional to the input phase difference, and may contain significant signal energy at the reference clock rate and at clock harmonics. These must be filtered out, typically before driving a VCO in a PLL application. The tuned phase-frequency detector output signal includes the instantaneous phase difference information only; it does not contain reference frequency or harmonic content.

    However, the penalty for this is that the timestep must be less than one-half the reference period, and typically less than one-tenth the period. To avoid the large amount of time jitter and phase noise that would normally be introduced by sampling at even these rates, the two digital outputs are also amplitude modulated to reflect the portion of a simulation timestep where the actual outputs would be high or low. For example, if based on the threshold-crossing timing (the pulse width should be 10 nsec, but the simulation timestep is 1µ), then the output amplitude for that timestep would only be 1% of the Vhigh level. While this will not properly model all the higher harmonics of the reference feed-through, it does accurately model both the dc term and the first few harmonics, and the corresponding reference sidebands of the VCO. As the analysis timestep is further reduced, the behavior becomes more truly digital in nature and more harmonics are effectively being simulated at the cost of slower simulations.
  4. The trigger times for both inputs is determined by detecting when the baseband voltage rises through the 0.5V threshold. Linear interpolation is used to get much finer time resolution than the analysis timestep. To further reduce excessive sampling jitter, the inputs to this detector can be sawtooth waveforms. While the detector will work reasonably well with sinusoidal inputs, given a small enough timestep, timing jitter can be eliminated if the interpolation is done on the positive slope of a sawtooth waveform. This is the reason why the divide-by-N models output a sawtooth waveform when they operate in the baseband mode. Square-wave inputs should generally be avoided, because this will usually introduce significant timing jitter and phase noise into the simulation.
  5. This model does not include any effects due to the finite duration of the flip-flop reset pulse and resultant zero-phase dead zone. Other effects, such as asymmetry between the two different outputs, can be incorporated by changing the external components. PhaseFreqDet Example shows an example using this detector; Output Waveforms shows the output waveforms.

PhaseFreqDet Example

Output Waveforms
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