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ParallelSerial (Parallel to Serial Shift Register)

Symbol

Available in ADS

Parameters

Name

Description

Units

Default

OutputRate

Serial output data clock rate

kHz

50

LSB_First

Select output serial data order:

None

yes

Delay

Initial synchronization delay

nsec

0.0

InputBits

Number of bits in input word

None

4

IntegerIn

Scale input data as integers: yes or no

None

yes

Notes/Equations
  1. This Parallel To Serial Shift Register model is used to convert a sequence of input words into a serial output bit stream. The fixed serial output bit rate is specified by the OutputRate parameter. The serial data can be output with either the LSB or MSB first, depending on the state of the LSB_First parameter. The output impedance is fixed at 0.1 Ohm. A logic one generates an open circuit voltage of 1.0V. A logic zero is 0.0V.
  2. The number of bits in each input word is specified by InputBits. The input is sampled at a rate equal to OutputRate/InputBits, with an initial synchronization delay specified by Delay.
  3. The input impedance is infinite. If the IntegerIn parameter is set true, then the input is assumed to be scaled as an integer from 0.0V to 2 OutputRate −1V. Otherwise, the input is assumed to be scaled from −1.0 to +1.0V, with −1.0V interpreted at word 0.
  4. This model works in transient and circuit envelope simulation. Only the baseband portion of circuit envelope voltage is used.
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