The PLL error when connecting 10MHz out of 33220A to 10MHz in of 33522B

The PLL error when connecting 10MHz out of 33220A to 10MHz in of 33522B

Troubleshooting (FAQ)

Summary

Explain why the PLL error appears when connecting 10MHz out of 33220A to 10MHz in of 33522B.

Question

The PLL error appears when connecting 10MHz out of 33220A  to 10MHz in of 33522B. However it works well when connecting 10MHz out of 53220A  to 10MHz in of 33522B.
Why?

Answer

It should be external lock.

A pll error, stands for phase lock loop,  error.  The 33220A timebase is not nearly as accurate as the 33522B timebase.  

You will get a pll error if the clock connected to the 33522B is not within 20 Hz of 10MHz.  If you have the OCXO option in the 33522B, the window is even tighter, you will get an error if the clock is not with in 1Hz of 10MHz.

In this situation, you can use the 33522B timebase as the master clock, and have the other instruments synchronize to it.