Solder Bumps


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Solder Bumps


Contents


Introduction

Abstract:Solder bumps are simulated with 3D FEM in ADS utilizing the 3D EM Component capability.Solder/wafer bumps have become popular for interconnect design in recent years because of their small form factor. They are used for connecting face-down IC chips onto substrates, circuit boards, or carriers in applications such as flip-chip, Chip Scale Package (CSP), and Wafer Level Packaging (WLP). In contrast, solder balls, which are almost identical but bigger than solder bumps, are typically used for ball grid array (BGA) packages.


Figure 1: Photo and 3D models of typical solder bumps

Design Challenges

Increasing operating frequencies and data rates, along with decreasing bump sizes, result in coupling / cross-talk between bumps, and between chip and board. IC and package designers must carefully characterize this coupling before the chip is taped out. This is especially true for CMOS applications where the fab process cost is extremely expensive. By re-arranging and optimizing bump layout early in the IC design process, problems can be avoided later.

Traditionally, designers analyzed 3D components, such as solder bumps, in a separate 3D EM design tool. The 3D EM results were then typically imported back to the circuit design environment for circuit simulation. This approach can be a tedious, error prone process in which designers have to learn multiple design tools to get the job done.

The best way to optimize a design is to dynamically analyze the EM effects along with the chip design (chip/package co-design). In this example we highlight the use of 3D EM simulation directly integrated with the circuit design environment, to speed the design process.

In ADS, a 3D component library can be installed as a design kit (link to design kit download at the bottom of this page). Solder ball components can then be placed in the ADS layout and a full 3D EM simulation can be run on the combination of the 3D solder balls and the planar layout design. The results can then be included in a schematic simulation. This design flow is summarized in Figure 2.


Figure 2: Design flow utilizing 3D components and 3D EM simulation in the ADS circuit design environment

Results

FEM simulations were run in ADS on a design example that includes 3D solderball components. Figure 3 shows the layout stackup in ADS and the 3D view of the design.


Figure 3: ADS layout stackup and 3D view of design including solderballs

S21 simulations with the ports set up at different solder balls will give us the isolation between these solder balls. In Figure 4 we see that the isolation in this example becomes less than 20dB starting at 14 GHz.


Figure 4: Simulated isolation between solder balls

In order to further analyze the isolation, we can examine the E-fields generated from the 3D FEM simulation in ADS.


Figure 5: FEM mesh and E-field results

Conclusion

Parameterized 3D components in ADS enable designers to simulate the effects of 3D solder bumps and improve their overall IC/packaging design.

Related Information

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