RFIC 60 GHz WiGig design integrated with integrated antenna array

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RFIC 60 GHz WiGig with integrated Antenna Array



Abstract :
RFIC design for mm wave 60 GHz WiGig requires EM analysis of both on-chip and off-chip wafer level packaged components and nets; plus integrated antenna array

RFIC design for mm wave applications such as WiGig, Automotive Radars and 5G components requires accurate EM simulation of on-chip components such as inductors and off-chip transitions to redistribution networks and integrated antenna arrays.

This example shows the multi-technology assembly of a beamforming RFIC from Cadence Virtuoso with signal splitting redistribution network and 8x8 path antenna array in ADS.

Layout vs Schematic (LVS) and Design Rule Check (DRC) across this multi-technology assembly are performed by ADS to verify a producible design.

Finally, RFPro enables automated error-free EM simulation setup of any selected on-chip and/or off-chip components and nets without modification to the layout to preserve design integrity. This can also include integrated antenna array to verify that RFIC,-wafer level package, and antenna can all work together before hardware fabrication. 

Design Challenges

On-chip frequency sensitive components such as inductors and capacitors in RFIC design need to be simulated with electromagnetic simulators. This basic requirement is often complicated by having to modify the original IC layout to extract and export the component to the EM simulator for analysis. Before the EM analysis can start,, EM, ports,  material properties and simulation parameters must be set up properly. After simulation, the multi-port S-parameter results must be manually stitched back into the original RFIC circuit to simulate with the active circuitry within Cadence Virtuoso. This can easily cause manual entry errors and risk design database corruption.

Figure 1 shows a better way to do this is with RFPro which provides EM simulation within Virtuoso on any passive component and/or nets without layout modification, thereby guaranteeing design database integrity,

Figure 1. RFPro integrated within Cadence Virtuoso allows spontaneous EM simulation of components and nets without any layout modifications.

RFIC design also need to account for off-chip wafer level packaged components such as couplers, splitters and integrated antenna array. This requires an environment to support assembling and routing of multi-technology components that may be placed adjacent, stacked or flipped; each with different technology layer mappings.

Figure 2 shows the assembly of the flipped RFIC between two wafer level package layers. The L1 layer contains the couplers and splitters needed to feed the phase array on layer L2. This is performed in Advanced Design System (ADS) using Smart Mount technology which enables any custom mount configurations to be assembled without having to modify layer mappings or substrate definitions of the assembled components. This preserves design database integrity and also sets up the layers and material properties for subsequent EM simulation of any chosen components and nets.

Figure 2. ADS Smart Mount enables assembly of stacked, adjacent and flipped technologies without modifing layer mappings or substrate definitions for subsequent EM analysis.

Routing of multi-technology assemblies above can be tedious, error-prone and ideally requires 3D avoidance routing with 3D visualization to ensure proper manual placement of interconnects.

Figure 3. shows the 3D avoidance interconnect routing with visualization in ADS to connect the RFIC with wafer level package layers L1 and L2.

Figure 3. 3D RF avoidance routing in ADS enables complex multi-technology RF module to be routed with 3D visualization all along the way to ensure no mistakes.

Layout vs. Schematic (LVS) and Design Rule Check (DRC) must be performed after 3D interconnect routing to ensure no mistakes prior to hardware fabrication.

Figure 4. shows ADS multi-technology Assembly Design Kit (ADK) which implements Layout vs. Schematic (LVS) and Design Rule Check (DRC) rules so that interconnect routing across stacked and adjacent components on multiple wafer level packaging layers can be automatically checked for correctness before hardware fabrication. 

Figure 4. ADS Assembly Design Kit (ADK) implements Layout vs. Schematic (LVS)  and Design Rule Check (DRC) for 3D multi-technolgy wafer level integration  of RFIC, antenna array and signal splitting networks.

RFIC designers need to quickly determine the impairments caused by the routed interconnects, transitions and the performance of off-chip components by using full 3DEM simulation. Traditionally, this is very tedious because the structure to be simulated must be manually extracted with re-assignment of ports, layers and material properties for a dedicated 3DEM solver to analyze. Fortunately, RFPro has automatic net and component extraction to enable 3DEM simulation of the extracted structure whenever required without modifying the assembled layout as shown in Figure 5.

Figure 5. RFPro in Advanced Design System enables spontaneous automatic extraction of any selected interconnets and components for EM simulaiton without modification to the original layout to preseve design database integrity. The results of EM simulation are automatically reconnected back into the circuit design to avoid manual stitching errors.


With the integration of RFPro in Cadence Virtuoso and ADS, it is now possible to EM simulate selected on-chip and off-chip components or nets spontaneously during the course of RFIC design to see the effects of tweaking component parameters or layout geometries. Hence, RFPro enables electromagnetic simulation to be used as an iterative design tool instead of a one-time sign-off verification tool. Compared to traditional non-integrated 3DEM simulators, RFPro saves 2 weeks to 2 months of manual preparation of the layout for EM simulation and re-stitching the EM results back to the RFIC simulation. 

ADS enables the multi-technology assembly and interconnect rounting  of RFIC, wafer-level package and antenna array with LVS and DRC checking of the entire assembly. This is the most efficient workflow to design RFIC with wafer level packaging of off-chip components with antennas for 5G, automotive radars and other mm wave applications.

Figure 6: ADS with integrated RFPro enables spontaneous 3DEM simulation of any single (e.g. rat race coupler and balun as shown on right) or multiple components and nets. (e.g. routing network for phased array signal splitting on left).  

Figure 7: RFPro Full 3DEM simulation of 16 phased array elements including 16 IC-Package-Antenna transitions in 4½ hours with 36 GB ram using default EM simulator settings. 

Figure 8: Antenna array far field radiation from equal excitation of 16 array elements. Can also use circuit simulation results with relative magnitudes and phases for circuit-EM excitation to gain insights on array  beamforming performance.

Acknowledgements: This 60 GHz WiGig design was created by Global Foundries and Fraunhofer IIS/EAS/IZM with EM simulations done by Keysight Technologies. 


  • RFIC design for mm wave applications requires spontaneous access to EM simulation as part of the iterative design process and not just for a one time verification sign-off because on-chip and off-chip passive components and interconnects can introduce significant frequency shifts and losses that must be accounted for during design. 
  • RFPro integration in Cadence Virtuoso and Keysight Advanced Design System makes this possible because of its automatic component and net extraction for efficient EM simulation without having to modify the layout. or manually re-stitch the EM data back into the RFIC circuit for EM-circuit cosimulation. It also preserves design database integrity.
  • This eliminates 2 weeks to 2 months of manual setup and re-import of EM results from using traditional standalone EM simulators.

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Meta Description

DocOwner:How-Siang Yap
Keywords:EM, RFIC, FOWLP, WiGig, mmWave, RF Module, RFPro, Integrated Antenna Array

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