RF Module Fan-Out Wafer Level (FOWL) Packaging


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RF Module Fan-Out Wafer Level (FOWL) Packaging


Contents




Introduction

Abstract :
RF Module assembly and interconnect routing of multi-technology silicon RF transceiver and GaAs filter on a Fan-Out Wafer Level Package (FOWLP). Automatic RF net extraction with RFPro enables critical signal paths through 3D interconnects to be efficiently analyzed with EM-circuit cosimulation without layout modification.


5G and automotive radars are increasingly operating in the millimeter wave frequencies from 28 Ghz to beyond 70 GHz. RF modules operating at these frequencies require low loss and low parasitic interconnects and packaging. One such solution is Fan-Out Wafer Level Packaging (FOWLP) where traditional wire bonds between chip and package are replaced by wafer level redistribution layer (RDL) interconnects. The design tool for these RF modules must be able to assemble, route and simulate such a multi-technology structure involving different IC technologies (Si, GaAs, GaN, SiC, etc.), RDL, fan-out laminate packaging and PCB solder bumps. Once assembled, the layout should not be modified for design integrity to enable EM or EM-circuit co-simulation of critical RF nets and components. This application example demonstrates how ADS is used for RF Module assembly and interconnect routing with FOWL packaging; and RFPro to setup, auto-extract RF nets and components, and running EM-circuit cosimulation to understand the effects of packaging between the Si IC transceiver and GaAs filter.

Design Challenges

Millimeter wave applications such as 5G and automotive radars with multiple chips in an RF module demands packaging and interconnects with lower parasitics than traditional laminate-wire bonding techniques. Wafer level packaging such as Fan-Out Wafer Level Package (FOWLP), Wafer-Level Chip Scale Package (WLCSP) fan-in with embedded Wafer Level Ball Grid Array (eWLB) are used in this example. The design challenge is to efficiently assemble, route and simulate such structures as shown in Figure 1.



Figure 1. RF module integrating Si, GaAs RFICs with fan-in WLCSP, eWLB array & FOWLP packaging.

Assembly of complex multi-technology RF modules for design and simulation has to accommodate adjacent, stacked and flipped chips with different technology layer mappings. Figure 2 shows how the perimeter pads of the Si transceiver IC is flipped onto the fan-in WLCSP with embedded Wafer Level Ball Grid Array (eWLB). This is easily performed using Smart Mount technology in Advanced Design System (ADS) enables any custom mount configurations to be assembled without having to modify layer mappings or substrate definitions of the assembled components. Therefore, this is suitable for large scale assemblies and stacked technologies.



Figure 2. ADS Smart Mount enables large scale assembly of stacked, adjacent and flipped technologies without the need to modify layer mappings or substrate definitions.

Interconnect routing across stacked and adjacent components assembled on multiple wafer level packaging technologies can be tedious and error prone. Fortunately the 3D avoidance RF routing technology in ADS enables this to be done easily with 3D visualization of the routed interconnect to verify correct placement all along the way as shown in Figure 3.



Figure 3. 3D RF avoidance routing in ADS enables complex multi-technology RF module to be routed with 3D visualization all along the way to ensure no mistakes.

RF Module designers need to quickly determine the impairments caused by the routed interconnects by using full 3DEM simulation. Traditionally, this is very tedious to do because the interconnect structure must be manually extracted with re-assignment of ports, layers and material properties for a dedicated 3DEM solver to analyze. Fortunately, RFPro has automatic net and component extraction to enable 3DEM simulation of the extracted structure whenever required without modifying the assembled layout as shown in Figure 4.



Figure 4. Automatic net and component extraction by RFPro enables spontaneous 3DEM simulation of the extracted structure without any modification to the original layout.

Results

RFPro 3DEM simulation results of the mismatch and losses introduced by the interconnects between the Si transceiver and GaAs filter are shown in Figure 5. RF Module designers can now spontaneously check for performance degradations caused by interconnects using the integrated RFPro 3DEM simulation in their circuit design flow.



Figure 5: ADS with integrated RFPro enables spontaneous 3DEM simulation of interconnect structures in the RF Module circuit design flow.

Conclusion

  • ADS and integrated RFPro makes the design, assembly and 3DEM-circuit co-simulation of RF Modules in WLCSP & FOWLP packaging efficient and error free. This is because of RFPro’s automatic extraction and setup of RF nets and components for accurate 3DEM simulation in the circuit design flow.

Related Information

More Information

Meta Description

DocID:
DocOwner:Jack Sifri, How-Siang Yap
DocCustViewable:Yes
Keywords:EM, RF_Module
DocVersion:RFPro2019
DocPlatform:RFPro

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