Back to ADS 2014.01 Release Notes
New Platform Features
ADS Board Link
ADS Board Link (ABL) is a new import/export tool that supports design and library information transfer between ADS and other third-party design environments. ABL supports import and export of all the following ADS library features.
- Technology information including units, resolution, layers, purposes, and substrates
- Schematic, layout, and symbol views
- Basic layout view shapes including polygon, polyline, trace, path, wire, rectangle, and circle
- Net and property settings for above shape objects
To enable Agilent Board link features, see ADS Board Link Installation.
Silicon RFIC Interoperability
Silicon RFIC Interoperability allows ADS to edit and simulate designs created in Cadence Design System's Virtuoso software and vice-versa. Silicon RFIC Interoperability is in a beta state for ADS 2014.01 as it depends on the availability of an enabled Virtuoso baseline PDK. We are providing a generic PDK on demand that allows you to explore this new functionality along a documented tutorial (see link below). We are working with silicon foundries to build out a portfolio of supported PDKs. Please refer to the EEsof Foundry Support page for latest updates on available ADS/Virtuoso front-end Interoperable PDKs or contact your local Agilent EEsof field person or firstname.lastname@example.org, if you have a specific request.
The following list are the specific commands that have been added as part of the Silicon RFIC Interoperability in this release.
- Edit CDF component definitions using the File > Design Parameters menu on a design window. Callbacks can be inline expressions or functions written either in AEL or Lisp.
- Edit component instance parameters that are in CDF format. Use the Edit > Component > Edit Component Parameters menu or double-click the instance.
- From the Main window, Options > Preferences has a new "Interoperability" tab that allows the user to choose defaults for editing of features related to IC Interoperability. "Legacy mode only" will use the defaults from ADS 2012.08 and before. "Interoperable mode only" will use defaults for compatibility with Open Access. "Combined legacy and interoperable modes" allows the user to choose how certain objects will be edited.
- New dialog for inserting Pins with various shapes. From Schematic, select the Options > Preferences menu, go to the "Placement" tab, enable the "Show Create Pin Dialog Box" checkbox, and then use the Insert > Pin menu.
- New dialog for editing existing Pins. Use the Edit > Pin menu or double click the Pin.
- New menu and dialog for adding symbol labels on a Symbol window. See the Insert > Symbol Label menu.
For more details, see Tutorial:Creating an Interoperable Schematic Design in ADS.
Connection Manager Client use of Command Expert
The Connection Manager Client can now use Command Expert instrument API to make S-Parameter measurements on PNA and ENA instruments without having to use Connection Manager Server. This allows you to make measurements without having to use a XP virtual box. The Command Expert mode can be toggled off and on using the Help > Toggle Use of Command Expert.
For more details, see Using Command Expert mode in Connection Manager Client.
New Layout Features
Support for Native Vias
Vias provide connectivity between different layers by joining two or more metal layers. Vias are important when you are working with multiple metal layers. From ADS 2014.01 onwards vias are introduced as OpenAccess (OA) objects, whereas earlier they were components. Via objects can be defined in two ways: rectangular and customized vias.
Following are the features of ADS 2014 vias.
- Uses native (OpenAccess) via definitions that are interoperable.
- Complex via structures such as arrays of rectangular cut vias for RFIC design are automatically created.
- Reduces setup time as it is easy to define and use vias.
- Via gets resized according to the trace width during trace insertion.
- Supports pin-less vias in layout that do not clutter the schematic.
- Supports backward compatibility of vias - Vias created in earlier releases as components can be used as OA via objects in ADS 2014.01. For more information on difference between ADS 2014.01 and earlier vias, see ADS Layout Differences.
For more details, see Via Definitions.
You can also use the sample rectangular and customized vias defined in Non-Linear Demo kit technology.
ADS 2014.01 introduces planes that allow you to create a layer of copper foil carrying a particular signal on a printed circuit board (PCB). A plane can be generated as ground plane or as signal plane.
You can create a plane:
- Using an existing shape.
- Inserting or drawing a new polygon.
Supports the following options:
- Clearance - Creates an appropriate clearance from shapes on different nets, while connecting to shapes on the same net.
- Thermal Relief - Creates thermal relief ties to avoid overheating of components.
- Smoothing Options - Enables you to smooth acute angles and remove notches.
- Plane regeneration - Enables you to edit and regenerate the plane. For example, if you move the plane from one location to another, the shapes on the plane automatically gets updated when the plane is regenerated.
For more details, see Planes.
New Layout versus Schematic (LVS) Features
- LVS based on physical properties of the layout.
- Recognizes devices, device pin connections and physical nets from the mask layers in the layout.
- In addition to checking for missing components and nodal mismatches, LVS will also check the device pin count against the device definition.
- Parameter values are calculated based on the physical properties of the device artwork.
- The layout will be flattened automatically prior to performing device recognition.
- Transmission lines are automatically removed from the schematic.
- LVS with Device Recognition requires a rules file, usually provided by the foundry.
- The EEsof Non Linear Demo Kit (ships with ADS) shows the recommended use model for writing rules.
- Requires the Advanced Layout License.
- Checks module level wiring.
- Detects pin swap errors.
- Supports connectivity through bond wires.
- Full hierarchical LVS.
- ICs can contain fixed layout artwork or nested technology.
- Requires the Advanced Layout License.
Components with Pin Nets
- Identify LVS errors using information in the design (components and pin connections).
- Enhanced with improved detection of shorts
- Displays a warning if there is discrepancy between nodal and physical connectivity.
- The discrepancy can indicate a connection that is not factored into the LVS comparison.
- Examples include interconnect that overlaps component artwork and interconnect that overlaps other interconnect without a connect dot.
- Browser format makes it easy to highlight and inspect errors.
- Report is automatically written out to a text file when LVS is run.
- The designer can select one or more analyses to run, depending on the approach that best suits the design.
- Device Recognition uses physical connectivity, whereas component-based LVS requires components and pin connections in the layout.
- If the layout has been created using library elements (components with layout artwork) the design will support running multiple types of LVS analysis. The designer can run Device Recognition and/or Component-based LVS every time LVS is run.
For more details, see Layout Versus Schematic (LVS).
New EM Simulation Features
Automatic EM/Circuit Partitioning
The Automatic EM/Circuit Partitioning facilitates the simulation setup when a layout contains instances that cannot be simulated by the EM simulator (e.g. a non-linear device) or for which a model already exists (e.g. a built-in simulator, schematic, or EMPro model). It obsoletes the manual process of creating intermediate cells for the EM model extraction and the painful and error-prone reintegration of the multi-port EM model in the testbench schematic.
For more details, see EM Circuit Cosimulation.
Other Enhancements and Improvements
- New '3D View' button on EM Simulation toolbar. This is the fastest way to view the layout 3D. EM specific pre-processing steps will be bypassed. Note: the '3D EM Preview' button performs all (EM-simulator specific) pre-processing as specified in the current EM Setup view.
- Port Editor
Port definitions are stored on the layout view. In ADS 2014.01, the port editing is done from the Layout window.
- New EM > Port Editor... menu and EM Simulation toolbar button to open the Port Editor from the Layout window
- New Port Editor toolbar button/right click menu to automatically set the nearest minus pin. The search for a suitable reference pin can be restricted to a net, a layer:purpose pair, or within a distance from the plus pin or a combination thereof.
- New Port Editor toolbar button to modify the calibration type for all or selected ports.
- New AEL function, db_set_port_definitions() to define ports as part of an AEL artwork macro.
- EM Setup
- New Tools > Open Symbol Editor menu and toolbar button to open the symbol view for the cell. In case of an empty view, the Symbol Generator dialog will be opened automatically. In case the view already exists, click the 'Open Symbol Generator dialog' button on the Palette.
- The S-parameter Ports in the EM Setup window are view only. To edit them, click the Edit... button which will bring you to the layout window where they can be defined and are stored.
- New Preprocessor options:
- Merge standard via arrays: this option replaces the individual cuts of a standard via arrays by their hull.
- Ignore shapes on the following purposes: shapes on the indicated purposes are ignored. An application of this feature is ignoring dummy metallization shapes. Use spaces to separate the purposes.
- New Tools > Create SnP Schematic menu to create a schematic view with an SNP instance referencing the dataset and baluns when differential ports are defined.
- Layer and Shape specific mesh settings are respected when mesh reduction is enabled. Previously, mesh reduction ignored them. For example, a denser mesh on a specific layer was reduced away to the global mesh density.
- The port information is written into the intermediate dataset created during a simulation. Previously, that information was only written into the final dataset.
- Momentum configuration variables can now be defined on the EM Setup Options Expert tab. They will only be applied for that specific simulation and are stored with the EM Setup view so you know which ones were applied for the simulation.
- A warning is issued during a simulation when electrically large ports are found.
- The source excitation setup for a far field computation has been integrated in the 3D Visualization environment under the Solution Setup tab.
- Update of the FEM engines to a version used in EMPro 2013.07
- Various issue fixes in the EMPro-ADS integration flow
- 3D Visualization
- More information is shown in the Antenna Parameter dialog box, e.g. frequency, input power, efficiency,...
- New Data Display template for a 2D far field cut
ADS Design Flow Integration (ADFI)
- The ADFI file import has been integrated in the Main Window. Open File > Import > Design... and select the ADFI File Format. This saves the step of creating a dummy library with a layout cell view first.
- Imported designs with component instances have the automatic EM/Circuit partitioning preconfigured and an EM Cosimulation view ready to be used in a circuit simulation.
- New import options.
New Electrothermal Floorplanner Tool
The electrothermal floorplanner tool provides a simple interface for layout-driven thermal analysis, so the initial placement of heat source in a chip can be quickly analyzed to compute the resulting temperatures. It is available on Linux only.
For more details, see Electrothermal Floorplanner.
Circuit Simulation Enhancements
- Long-Term Memory Effects in X-parameter Models
ADS 2014.01 contains beta code for handling long-term memory effects in XnP components. This functionality is released in anticipation of the NVNA measurement capabilities to capture time-domain step response data. The term "step response" data refers to the time domain variation of the selected X-parameters when the magnitude of the input reference incident wave jumps from zero to a non-zero value at time t = 0. In order to use this feature, you will need a separate file containing the step response data. However, in ADS 2014.01, the X-parameter generator does not yet include the means to generate such files.
For more details, see Support for Handling Long-Term Memory Effects.
- Nonlinear Models
- DC Solver
- The default DC solver has been enhanced to include a new convergence algorithm that is suitable to large circuits that previously used to pose convergence difficulty
- Upgraded to support Accellera 2.3 Verilog-A standard for analog modeling via the latest 2.x Verilog-A/MS simulation component set provided by Tiburon Design Automation.
- Reduced compilation overhead, faster simulation boot, minimal compilation used for analog blocks only, compiled object sharing used to minimize overhead of commonly used modules
- Simplified use model for sharing compiled Verilog-A
- Verilog-A source encryption
- Verilog-AMS 2.x; support on both Windows and Linux
- Latest Angelov and Angelov-GAN Verilog-A models
New Verification Test Benches (VTB) for LTE, LTE-Advanced, WLAN 11ac, RADAR, and DigitalMod
New Verification Test Benches (VTB) ensure spec-compilant, complex-modulated verification for your RF designs to the latest wireless standards. ADS VTBs have a simplified, measurement-based user interface and are simulated using your current ADS Ptolemy license. The ADS Ptolemy license enables the underlying Agilent SystemVue VTB dataflow engine. ADS 2014 offers the following new pre-configured VTBs:
- W2390 LTE-A VTB Element
- W2388 LTE 3GPP VTB Element
- W2385 WLAN 802.11ac VTB Element
- RADAR VTB Element
- DigitalMod VTB Element
System architects can easily modify pre-configured VTBs or even create new custom VTBs using Agilent SystemVue, for use in ADS.
For more details, see Verification Test Bench.
High-Speed Digital Design
- New product W2307 ("Controlled Impedance Line Designer") Element lets you design single-ended and differential microstrips and striplines.
- These pre-layout transmission lines can be optimized for the metrics that matter (e.g. post-equalization BER contours) by optimizing the parameters from the context of Tx -> channel -> Rx simulation in Transient and Channel Simulators
- Large sinusoidal jitter
- At low frequencies, sinusoidal jitter can greatly exceed the unit interval (bit period)
- Channel Simulator can now model this, including the CDR’s ability to track and mitigate the impairment
- Eye Probe component can now send the post-CDR clock waveform to the data set.
- Two formats are written: ClockSignal and ClockSpike represent clock times at their zero-crossings and spikes, respectively
- The primary motivation for this new capability is to enable further analysis (e.g. jitter decomposition) in external software packages that require separate (post-CDR) signal and clock waveforms. An example is InfiniiView software, which is the offline version of the analysis software used in Agilent oscilloscopes
- If the Rx AMI emits clock times, these are used to create ClockSignal and ClockSpike. Otherwise, the Channel Simulator creates a perfect clock based on the specified bit rate.
- Line coding
- 64B66B and 128B130B line coding in Channel Simulator bit-by-bit mode (only)
- These are used, for example, in Ethernet and PCIe Gen 3 respectively
- Note that in this release, statistical mode still only supports “No encoder” and “8B10B” options, and not the new 64B66B and 128B130B modes that bit-by-bit mode now supports
- Impulse Response Caching
- Gives ~4X speed improvement in certain Channel Simulations, for example those that use multi-layer model library channel models
- IBIS 5.1 parser
- Some IBIS 6.0 features are also supported
- More details about support of traditional IBIS (based on Transient Simulator) and IBIS AMI (based on Channel Simulator) are given in About IBIS Models.
- ADS requires: a) the version 2018.04 of the EEsof EDA licensing software, b) a minimum code-word version 2018.04 or above, and c) the licensing server software, lmgrd and agileesofd, to be upgraded to at least the same versions as what are included in EEsof EDA Licensing software 2018.04. ADS All-Versions will not start if any of these requirements is not met. Refer to the License Codeword Version Compatibility Table.
- In the EEsof EDA License Tools version 2018.04, licensing vendor daemon (agileesofd) is integrated with FlexNet FNP 18.104.22.168 version (Windows) and FlexNet FNP 22.214.171.124 version (Linux) of FlexNet license manager daemon (lmgrd). For the Windows platform, ADS installer will automatically set up these two new license server daemons by default for the local node-locked license users; for the Linux platform, you need to follow the Linux Licensing Setup instruction to complete the licensing configuration process. For more details, refer to Licensing (For Administrators).
The Advanced Design System installation configuration has been updated on both the Windows and Linux platforms
- On the Windows platform, there are now two separate ADS installers, one installer support the 64-bit version of Windows, and the other installer support the 32-bit version of Windows.
- On the Windows platform, the default ADS installation location is
- On the Linux platform, the ADS installation only delivers 64-bit versions of the ADS binaries files. Cadence customers are recommended to upgrade to Cadence 6.1.4 or 6.1.5 and run Cadence in 64bit mode, or use ADS 2013 and earlier for running Dynamic Link with 32bit Cadence virtuoso, msfb, or icms.
- ADS LAN Client files are now under a separate download only file named
LAN_client_setup.zip. Following is an example of how to install and use the ADS LAN Client setup with in a command prompt.
- Download the file
- Copy the file
LAN_client_setup.zipto the ADS installation directory.
- Change directory to the ADS installation directory.
- Unzip the file LAN_client_setup.zip, example:
setup.exefrom the unzipped LAN_client_setup folder.
- Download the file
New HDF5 File Format Export Support
A new AEL expression called write_hdf5() has been added to allow the export of dataset and expression results into HDF5 file format.
- Search Tips have been added to help you search effectively.
- QR Code feature added for quick download of EPUBs on mobile devices.
New Application Based Flows and Tutorials
Application Based Flows
- Power Integrity (PI) Analysis using Momentum
- SI/PI Analysis of 16 Data Signals using IBIS Power BIRDs
- End to End Link Analysis using Retimer AMI Model
- Creating an Interoperable Schematic Design in ADS and Virtuoso
- Using the EM Cosimulation View
- Controlled Impedance Line Designer Tutorial