ADS 2009 Update 1 Release Notes
To install ADS 2009 Update 1, please refer Quick Installation documentation for this release.
For details on what's new in ADS 2009 Update 1, refer to the product page at
For general ADS information, refer to the Agilent EEsof product page at
What's New in ADS 2009 Update 1
ADS: The Hi-Frequency & Hi-Speed Platform for IC, Package and Board Co-Design
ADS 2009 Update 1 delivers new features and improved value for all ADS users with special focus on MMIC and RF Module design, including a Complete MMIC ADS Desktop Flow to manufacturing. These new features eliminate the time to integrate disparate point tools from numerous vendors (e.g. 3D EM, Layout, DRC & LVS).
- New X-Parameter Generator — creates fast, IP-protected nonlinear models
- Enhanced Integrated 3D EM Analysis — including Finite Element EM sweeps, optimization and co-simulation with circuit analysis
- Complete MMIC ADS Desktop Flow to Manufacturing — including enhanced PDKs, ADS Desktop LVS and Calibre LVS integration
- New Optimization Cockpit — interactively monitor, tune and guide optimizations for better results, faster
- Signal Integrity Channel Simulation and Eye Diagram Statistics
- Dozens of other improvements to the circuit & EM simulators, models & libraries, and the ADS Core platform including layout & data display
NEW Generate X-Parameter Models from Circuit-level Designs
- Simulation speed up
- Faster system simulation & verification than circuit-level models
- Simulation accuracy
- Unprecedented accuracy of non-linear behavior in phase and magnitude at all harmonics.
- Models can be cascaded, load pulled, and will account for mismatches
- Fully functional behavioral models (IMD, mixing product, spurs, higher order harmonics)
- New method for IP sharing - both safe and highly efficient
- Replaces the labor-intensive, conventional datasheet creation with push button model generation
- Consumer simply drags and drops model into design and instantly can simulate within a system design
- Makes it possible to secure design wins, even before physical parts are available
- Automatically provides IP Protection
NEW X-Parameter Generator Details
- Generate nonlinear X-parameter models in ADS
- Augments Agilent's measurement-based X-parameter generation (PNA-X Series Nonlinear Vector Network Analyzer)
- Easy to setup and run
- No limits on frequency, power, or number of ports
- Multi-tone support
- Models amplifiers, mixers and transceivers with frequency conversion.
- X-parameter simulation is now even faster
- Up to 100x faster than previous version
NEW Optimization Cockpit - Automation enhanced with the Designer's Expertise
- Single interactive cockpit view of optimization puts everything at your fingertips
- Error function of each goal
- Progress of desired response
- Optimization variable sliders
- Enables interactive tuning during optimization
- Variable history provide insights to adjust limits
- Provides user with the control to guide the optimization to even better results
- User can pause the optimization at any point
- While paused, change the goals, limits, number of iterations, variable ranges, even the actual optimization algorithm
- Then simply push a button and the optimizer will continue where it left off
NEW MMIC Layout Toolbar
- Makes layout editing commands work with foundry-defined metal layers
- Provides easy access to a full suite of layout verification tools
- The MMIC Toolbar is available in enhanced foundry PDKs
- Backward compatible with ADS 2009 release
- Toolbar features
Improved Load Pull FrontPanel
- NEW Load Pull FrontPanel Features
- NEW Easily import multiple, single dimension load pull files
- NEW Supports contour plotting for frequency and power sweeps
- Improved usability and performance
Major Improvements in Physical Verification
- NEW Mentor Graphics Calibre LVS integration provides foundry-level compliance
- Easy push-button launch from inside ADS
- Supports Calibre RVE interactive environment
- Cross-probe between RVE and ADS schematic and layout
- NEW ADS Desktop LVS - Catch errors early in the design process
- Checks equivalent components in schematic and layout
- Checks circuit mismatches
- Checks parameter mismatches
- Supports netlist equivalents for EM components
- Analyzes the full design hierarchy
- Can compare schematics and layouts from different designs
- Generates a component count
- Improved ADS Desktop DRC
- NEW General Math Functions for more sophisticated error checking
- NEW Text Markers make it possible to embed more intelligence into the design
- NEW Status Window to track DRC execution
- Improved Results Viewer makes it easy manage which errors have been checked
- Significantly faster Boolean functions delivers up to 2X overall performance improvement
NEW Package Assembly Tool
- Simplifies the setup of a stacked multi-substrate environment
- Makes it possible to model and simulate effects across physical boundaries
- Can be used with EMDS G2 or Momentum
- Backward compatible with ADS 2009 release
Continued Improvements to Integrated EM Simulation
- Momentum Simulator
- FEM Simulator (EMDS G2)
- Improved user interface & easier setup
- Improved handling of thick metal
- Better meshing of curved surfaces
- Improved loss modeling at low frequencies
- NEW linear basis functions improve performance by up to 10X for electrically small complex structures.
- 3D Viewer
- Push button 3D window update
- NEW Select and display physical connectivity in 3D Viewer
More Ways to Utilize Agilent's World-Class EM Technology
- NEW ODB++ import
- Improved Gerber & Drill file import
- Enhanced link from Cadence Allegro PCB Editor, Package Designer (APD) and SiP
- Now transfers wire bonds, die stacks, and more
- Dynamic Access for Mentor link now supported on Linux OS
New Features in Data Display
- NEW Antenna plot now in Data Display
- NEW dataset filtering - quickly find variables with just a few keystrokes
- NEW line markers provides an easy way to display values across multiple traces
- Faster trace selection
- Performance improvement for large number of output variables
- 64-bit simulators only
Enhancements in Verilog-A
- New LRM 2.3 support
- Support for analog initial block
- Support for dynamic enable of timer and cross events
- Improved LRM 2.3 string support
- string memory states
- strlen function
- string concatentation
- substrings function
Models & Libraries
- Updated Asia Digital Mobile TV Library
- CMMB Wireless Library
- Models based on the Mobile Multimedia Broadcasting specification (GY/T 220.1-2006).
- Provides signal patterns that comply with the specification.
- Provides transmitter measurements including waveform, CCDF, spectrum and EVM.
- DTMB Wireless Library model updates
- CMMB Wireless Library
- HSPA Wireless Library
- HSPA+ update for HSDPA and HSUPA Wireless Libraries
- Updated downlink source models with HARQ and AMC functions. Provides 12.2k 3GPP FDD reference channels and TestModel1 to TestModel6 for HSDPA downlink channels.
- Updated downlink receiver models capable of processing Hset1 to Hset8 and HS-SCCH.
- New downlink type 2 receiver (LMMSE)
- Updated uplink source models with HARQ functions. Provides uplink fixed reference channels FRC1 to FRC8.
- Updated uplink receiver models for FRC1 to FRC8.
- Core ADS Ptolemy Models
- New data flow Analog to Digital models: AtoD as a general purpose A-to-D and A-to-D_ADI for specific Analog Devices A-to-D models.
Continued Advancements in Signal Integrity
- Channel Simulator
- DFE and FFE support with automatic tap optimization
- Statistical simulation mode
- BER contour and bathtub display
- New eye mask utility with automatic violation checking
- Ability to check cross-talk for different data rates
- Many enhancements to the crosstalk element
- DDR3 Compliance DesignKit
- Expanded modeling capability now includes IBIS ECL Models
- NEW TDR FrontPanel
Improvements to Design Environment
- Improved click, selection, drag, and right-click, especially for overlapping objects
- New DesignContext AEL functions for more consistent AEL scripting capabilities.
- Better organized front end makes it easier and faster to find topic you are looking for
- NEW MMIC Overview quickly links you to documentation specific to the MMIC design flow
Circuit Simulation Fixed Issues
- The maximum size of an analysis header line has been increased. When the simulator runs an analysis, it writes a header line that includes the type of analysis, the dotted path of the analysis controller, and other information. The length limit for this line has been increased.
- Transient simulation capacitor initial condition values >= 1mF are now preserved.
- An error is issued when simulating port data that exceeds the number of ports for the S-parameter data device.
- A correct netlist is now generated when using a DynamicLink subcircuit from an included project.
- Simulation results for bsimsoi devices with a floating body now match with spectre.
- MixIMT_Data now supports wildcard values for RF and LO frequencies in A and B type IMT files.
- Improved accuracy of MixIMT_Data for very low values of RF power.
- Batch Simulation
- Results from multiple simulation controllers are now outputted.
- All datasets are placed in the "data" directory.
- NetlistInclude files can now be swept with CSV files.
- Several improvements when using Eye Probes.
- Spectre Compatibility
- Netlist include statements inside structural-if blocks are now handled.
- A mutual_inductor in a case-insensitive section is now able to correctly find the referenced instance using case-insensitive matching rules.
EM Simulation Fixed Issues
- The sparse solver interface has been upgraded to use full 64-bit integers to resolve memory allocation problems for very large problems.
- The layout resolution is always preserved after meshing.
- There is no need to recreate the Layout Component after an edit. It is sufficient to use Edit > Component > Update Component Definitions... from the top level design.
- Momentum > Substrate > Update From Schematic will handle negative values of T[ i].
- Non-convergence issues with the iterative solver on 64-bit Windows have been resolved.
- Improvements in low frequency loss modeling with thick conductors, resulting in accurate DC loss modeling
- Mesher robustness improved further
- Expansion problem for conductors and vias issues fixed, vias running through multiple layers and crossing expanded strip layers now provide correct connectivity
- Internal meshing in bondwires, resulting in accurate DC loss modeling
- Various improvements and fixes in EM visualization
- Improvements in 3D component flow, in combination with EMPro 2008.1 release, the use model for the setup and use of 3D parameterized components has been greatly improved.
Installation Fixed Issues
- For Windows the default user home directory has been changed on Vista to C:\Users\name which is the preferred location for Vista to avoid access permission problems during installation. This change only applies to Vista. On XP the user's home directory will remain C:\users\default.
- Users can now type in their desired HOME directory during the installation process in the "Set Your Home Directory" panel. Previously you were required to select a new location with the "Choose" button and subsequent file dialog if you wanted to set your HOME to be different than the standard default location.
Licensing Fixed Issues
- Users should be able to simply place a new uncounted node-locked license file in their "HPEESOF_DIR\licenses" directory and run ADS 2009 Update 1 without any further setup or configuration steps. This is now the case even when license settings from previous releases already exist. If more exact control over the license path is needed then there are now new menu items in the License Preference and License Information tool to allow easy modification of the license file path setting.
- A problem has been fixed where multiple bundles were sometimes pulled even when an existing bundle that was already checked out had licenses for the requested operation. This occurred when extended license searching was active which is the default mode of operation.
- A new menu bar has been added to the License Preference and License Information tools to allow you to display and change both the current license path setting and the extended license search setting. This can be even be done outside of ADS. These settings can be accessed from the "Options" menu of these tools by selecting "License Path Setting.. and "Extended License Search Setting...".
- The license path dialog shows the current location of your license servers and/or license files and allows you to make changes directly from the text entry field that is displayed. Note you will have to shutdown and restart any running sessions in order for the new settings to take affect.
- The extended license search dialog shows your current configuration even if you previously turned off informational dialog pop-ups. It allows you to turn on/off automatic extended license searching, the display of informational dialog pop-ups, and interactive bundle selection via check boxes.
Physical Design Fixed Issues
- ADS Desktop DRC
- A problem has been fixed where dve_import_cell_layer() rule was not working for design kit component having circular figures like via components.
ADS Platform Fixed Issues
- Library Browser now includes user (SITE) libraries.
- Simulation Variables Setup dialog correctly applies varying unit types.
- Performance has improved for Create Hierarchy.
- Selection has improved for overlapping components and components surrounded by a polygon.
- Reduced the size of the confirmation dialog when deleting a large number of files.
- Corrected the design traversal for Bill of Materials.
- Fixed problems with mapping commands to hot keys.
Documentation Fixed Issues
- Search works with all the Java Runtime Environment 6 versions including latest update 14.
- Search will work on all the platforms and supported browsers for both Windows and Linux.
- Improved error messages to help search keywords better.
Simulation Known Issues
8B10B Encoder Support in Statistical Analysis
8B10B Encoding constraints are not applied in the statistical analysis of the Channel Simulator. If statistical simulations are performed on channels with 8B10B encoder, results will be identical to those without encoder.
License Checking Order Has Changed
In ADS 2009 and earlier, the simulator would, by default, first look for the "sim_syslinear" codeword first, and then, if that was not found, "sim_linear" would be used instead. This default order has been reversed for ADS 2009 Update 1: the simulator now looks for "sim_linear" first, and "sim_syslinear" second.
This default order can be controlled through the use of the "
rf_cw_priority" simulation configuration parameter. To restore the old ADS 2009 and earlier search order, place the following line into either of the files, "
$HPEESOF_DIR/custom/config/hpeesofsim.cfg", or, "
Optimizing Channel Simulation Receiver, Transmitter, and Crosstalk Component Parameters Produces Invalid Results
Directly optimizing the parameters on the following device components will produce invalid results: Rx, Diff_Rx, Tx, Diff_Tx, Xtlk, Diff_Xtlk.
Use the VAR component to define the optimization variables, and then set the component parameters equal to the VAR component variables.
Connection Manager Known Issues
Connection Manager based ADS Ptolemy instrument links
These schematic based Instruments links are available on all supported platforms.
- For Windows exceptions, see Windows Installation documentation for Before You Begin Windows Installation page in the "Supported Features on Windows 64-bit" table.
- For UNIX and Linux exceptions, see UNIX and Linux Installation documentation for Before You Begin UNIX and Linux Installation page in the "Supported Features on 64-bit Operating Systems" table.
Connection Manager Client User Interface is disabled on Linux
The Connection Manager Client User Interface has been disabled on Linux since ADS 2008 Update 2. It still works on Windows and Sun Solaris.
Connection Manager Server cannot be installed on 64-bit Windows machines or 32-bit Windows Vista machine
Connection Manager Server must be installed only on a true 32-bit Windows XP or 2000 machines; it will not operate properly in 32-bit compatibility mode on 64-bit machines. The Connection Manager Server is not included with ADS 2009 Update 1. It is obtained from the ADS 2009 Update - Software Downloads web page.
On Windows XP, Connection Manager Server fails if Toshiba bluetooth driver installed
EDA00187795 — On Windows XP, the Connection Manager Server can fail if the Toshiba bluetooth driver is installed.
Uninstall the "Bluetooth Stack for Windows by Toshiba". Although the Bluetooth Stack for Windows by Toshba is uninstalled, XP still provides a Bluetooth capability. So, the alternative Bluetooth is still there.
Digital Filter Synthesis Utility Known Issues
The Digital Filter Synthesis Utility is no longer available in ADS 2009 Update 1. This feature has been removed from ADS and is replaced by superior capability in Agilent's new SystemVue product platform. Please contact your sales representative if you would like to take advantage of a special upgrade offer to the Digital Filter Design Tool in SystemVue.
Platform Specific Known Issues
EDA00201983 - DRC runs for long time for um designs.
Run DRC in Current window view mode. To run on full design use Layout=>View=>View all option before running DRC.
Documentation Known Issues
Hyperlinks to PDF files do not work on Windows machines using Internet Explorer 6x or above
In Microsoft Windows machines running Internet Explorer 6.x, there may be no response when a hyperlink to a PDF file is selected.
Occasionally this occurs because Acrobat Reader is not configured to open PDF files within the browser. (To check, open Acrobat Reader, click Edit > Preferences > Options, and make sure that the checkbox Display PDF in Browser is selected.) However, that is not usually the cause of the problem.
If PDF files will not open in the Internet Explorer browser, the problem is usually caused by a conflict between Adobe Acrobat and the security features of the browser. Although it is often possible to eliminate the problem by means of configuration changes, this approach is time-consuming and does not always work.
It is usually preferable to solve this problem by either of two methods:
- Use a different application (such as Netscape or Mozilla Firefox) as your default browser.
- Right-click on the link to the PDF file, and choose Save Target As from the right-click menu to save a local copy of the PDF file.
Not able to view Videos in 64-bit browser
Adobe Flash Player is not supported for playback in a 64-bit browser. However, you can run Flash Player in a 32-bit browser running on a 64-bit operating system.
For more details refer http://kb2.adobe.com/cps/000/6b3af6c9.html.
ADS Hangs with documentation access (HELP > Topics and Index) on Linux/Suse Platform
Firefox corruption or incorrect colsure of previous session leads to "Firefox is already open" error message or "Unable to Open Browser" situation.
To eliminate this, do the following:
- Go to <usr> directory
- Type cd mozilla/firefox
- Type rm profiles.ini
Verilog-AMS Known Issues
In ADS 2009 Update 1 connect modules in AMS should not be manually inserted
Use conventional module. For example, see the Test_Divider design in the VAMS_Examples_prj (located in the examples > Verilog-AMS directory
ADS Desktop LVS
This is the first release of the ADS Desktop LVS. We are very interested in hearing your feedback on this new capability. Please contact EEsof Technical Support with your feedback and suggestions.
ADS Desktop LVS Key Features:
- Detects component, nodal, and parameter mismatches.
- Component-count information makes it easy to detect missing components.
- Analysis is based on database comparison and does not require a rule deck.
- Can be run on any ADS design containing components (PDK library elements, hierarchical components or custom models).
- Designs do not need to be synchronized with ADS Layout/Schematic Design Synchronization.
- Selecting an error highlights the corresponding elements in schematic and layout.
- Supports a full hierarchical check.
- Can be used in combination with Design Synchronization but does not depend on it.
- Does not require instance names to be equivalent, but will potentially use this information to resolve ambiguities (especially for Ports).
- Can compare a layout and schematic from different designs.
- Can be run from either schematic or layout.
- Provides a component-count breakdown for foundry submission.
- Recommended Uses
- Layout Verification prior to Foundry Submission
- Use ADS Desktop LVS to validate that the schematic and layout are equivalent.
- Run with parameter check enabled to verify parameters are consistent (number of turns on a spiral inductor).
- Use the keyboard right arrow to expand the browser. Use the keyboard left arrow to contract.
- Layout Verification during Design Creation
- Use ADS Desktop LVS throughout the design cycle to find and fix errors early.
- Use the component-count information to quickly identify if a different number of components exist in schematic and layout. Correct these errors first before addressing nodal mismatches.
- Use the component-count information to inspect the location of components. Use the keyboard down arrow to step through each component type. The instances will highlight in the schematic and layout.
- Layout Verification for Team Design
- Use ADS Desktop LVS to check for consistency between a schematic and layout created by different designers or a layout created manually.
- Use ADS Desktop LVS to check for completeness during the integration phase (combining different parts of a design into one schematic and corresponding layout).
- Layout Verification after Design Generation
- ADS has the ability to auto-generate a layout from a schematic (and visa versa). (See Layout>Generate/Update Layout...). If you then edit either the schematic or layout you can use ADS Desktop LVS to check for component, nodal or parameter mismatches.
- Parameter Check
- Analyzing component parameters may require expressions to be evaluated and can take several seconds. You can chose to disable the parameter check when running ADS Desktop LVS.
- Schematic with Ports
- S-Parameter simulations require terminals connected to grounds whereas a layout will have Ports. To avoid having these appear as component mismatches, it is recommended that the schematic be pushed down one level of hierarchy. The schematic and layout will then have the equivalent number of Ports. To do this, select the circuit elements and execute the menu pick Edit>Component>Create Hierarchy.
- Layout Verification prior to Foundry Submission
Wireless Design Libraries
HSDPA Wireless Library
Top Level Models
- Top-level baseband signal sources and RF signal sources for downlink are provided. Various downlink signals can be generated using these top-level signal source models by setting their parameters. These are very easy to use. The functionalities are as follows:
- Downlink source with HARQ and AMC functions
- Fixed reference channels Hset1 to Hset8 are pre-configured.
- Downlink source also includes 12.2k 3GPP FDD reference channel and TestModel1 to TestModel6 for HSDPA downlink channels.
- Top-level baseband receivers and RF receivers for downlink are also developed. Corresponding to top-level signal sources, all these top-level receiver models have the same parameters as that of the signal source models. With these models, customers can create their system measurements very easily.
- Downlink receiver capable of processing Hset1 to Hset8
- Downlink receiver capable of processing HS-SCCH.
The HSDPA Wireless Library provides test benches for HSDPA transmitter and receiver measurements. Two projects (HSDPA_BS_Tx_prj, and HSDPA_UE_Rx_prj) are provided in this HSDPA WL.
This project provides receiver test benches of HSDPA downlink. The receiver measurements include Demodulation of HS-DSCH, HS-SCCH detection performance and Maximum input power.
- UE_Rx_Demodulation_Hset1_PA3_QPSK.dsn: Demodulation of Hset1 with QPSK under PA3
- UE_Rx_Demodulation_Hset2_PB3_16QAM.dsn: Demodulation of Hset2 with 16QAM under PB3
- UE_Rx_Demodulation_Hset3_VA30_16QAM.dsn: Demodulation of Hset3 with 16QAM underVA30
- UE_Rx_Demodulation_Hset4_PB3_QPSK.dsn: Demodulation of Hset4 with QPSK under PB3
- UE_Rx_Demodulation_Hset5_VA120_QPSK.dsn: Demodulation of Hset5 with QPSK under VA120
- UE_Rx_Demodulation_Hset6_PA3_16QAM.dsn: Demodulation of Hset6 with 16QAM under PA3
- UE_Rx_Demodulation_Hset6_VA30_16QAM_LMMSE.dsn: Demodulation of Enhance type 2 receiver for Hset6 with 16QAM under VA30
- UE_Rx_Demodulation_Hset8_PA3_64QAM_LMMSE.dsn: Demodulation of Enhance type 2 receiver for Hset8 with 64QAM under PA3
- UE_Rx_HSSCCH_Detection_TS1_PA3.dsn: HS-SCCH detection performance of test number 1 under PA3
- UE_Rx_Maxlevel.dsn: Maximum input level for HS-PDSCH
This project provides transmitter test benches for HSDPA downlink. The transmitter measurements are ACLR, CCDF, EVM, maximum output power, occupied bandwidth, peak code domain error, spectrum emission and connecting with VSA.
- BS_Tx_ACLR.dsn: Adjacent channel leakage(ACLR) of BS transmitter
- BS_Tx_CCDF.dsn: CCDF of BS transmitter
- BS_Tx_EVM.dsn: Modulation accuracy of BS transmitter
- BS_Tx_Max_Power.dsn: Maximum output power of BS transmitter
- BS_Tx_OccupiedBW.dsn: Occupied bandwidth of BS transmitter
- BS_Tx_Pk_Code_Error.dsn: Peak code domain error of BS transmitter
- BS_Tx_SpecEmissions.dsn: Spectrum emissions of BS transmitter
- BS_Tx_VSA.dsn: connecting with VSA
- For HS-PDSCH Discontinuous Transmission (DTX) with 64QAM, the results maybe incorrect for multiple frame EVM measurement.
- 2005A.401 - July 2006 (Initial release)
Initial release of HSDPA wireless library.
- 2008U2.401 - Feb 2009 (enhanced release for HSPA+ Tx for MTK)
New single link 64QAM modulated DL HS-PDSCH packet channel
New Test Model 6
New HS-DSCH physical category 13, 14, 17, 18
New FRC H-Set 7, 8
Updated EVM measurement function for downlink
- 2008U2.402 - March 2009 (enhanced release for HSPA+ Rx for MTK)
- New enhanced type 2 (LMMSE) receiver for downlink
- Support LMMSE equalizer with both ideal CSI (Channel Side Information) and real CSI (obtained from synchronization and channel estimation algorithms)
- New ITU channel model for ideal enhanced type 2 receiver performance testing with ideal CSI output (both delay and finger power)
- New enhance type 2 demodulation performance design for H-Set6 with 16QAM for downlink
- New enhance type 2 demodulation performance design for H-Set8 with 64QAM for downlink
HSUPA Wireless Library
Top Level Models
- Top-level baseband signal sources and RF signal sources for uplink and downlink are provided. Various downlink/uplink signals can be generated using these top-level signal source models by setting their parameters. It's very easy for customers to use. The functionalities are as follows:
- Uplink source with HARQ function
- Fixed reference channels FRC1 to FRC8 for uplink
- Fully-functional 3GPP FDD downlink source including HSUPA downlink channels.
- TTI 2 ms and 10 ms
- Top-level baseband receivers and RF receivers for downlink and uplink are also developed. Corresponding to top-level signal sources, all these top-level receiver models have the same parameters as that of the signal source models. With these models, customers can create their system measurements very easily.
- Uplink receiver for FRC1 to FRC8
- Downlink receiver for HSUPA related channels.
- Top-level RF measurement models for uplink are developed.
- Output power measurement
- EVM measurement
The HSUPA Wireless Library provide test benches of HSUPA transmitter and receiver. Four projects (BS_Rx_prj, UE_Rx_prj, UE_Tx_prj and HSUPA_RF_Verification_prj) are provided in this HSUPA DL.
This project provides receiver test benches of HSUPA uplink. The receiver performance measurements include E-DPDCH demodulation performance, E-DPCCH demodulation performance and False alarm possibility in AWGN channel.
- BS_Rx_Demodulation.dsn: E-DPDCH demodulation performance in AWGN channel
- BS_Rx_MissDetection.dsn: Missed detection possibility of E-DPCCH in AWGN channel
- BS_Rx_FalseAlarm.dsn: False Alarm possibility in detecting E-DPCCH in AWGN channel
- BS_Rx_DemodulationFading.dsn: E-DPDCH demodulation performance in fading channel
- BS_Rx_DemodulationFading_FRC8.dsn: E-DPDCH FRC8 demodulation performance in fading channel
- BS_Rx_MissDetectionFading.dsn: Missed detection possibility of E-DPCCH in fading channel
- BS_Rx_FalseAlarmFading.dsn: False Alarm possibility in detecting E-DPCCH in fading channel
This project provides receiver test benches of HSUPA Downlink. The receiver measurements include demodulation performance of E-AGCH, E-RGCH, E-HICH.
- UE_Rx_EAGCH_Demodulation.dsn: Demodulation of E-DCH Absolute Grant Channel (E-AGCH)
- UE_Rx_ERGCH_Detection.dsn: Detection of E-DCH Relative Grant Channel (E-RGCH)
- UE_Rx_EHICH_Detection.dsn: Detection of E-DCH HARQ ACK Indicator Channel (E-HICH)
- UE_Rx_EAGCH_DemodulationFading.dsn: Demodulation of E-AGCH in fading channel
- UE_Rx_ERGCH_DetectionFading.dsn: Detection of E-RGCH in fading channel
- UE_Rx_EHICH_DetectionFading.dsn: Detection of E-HICH
This project provides transmitter test benches of HSUPA downlink. The transmitter measurements are output power, EVM, spectrum emission, ACLR and CCDF.
- UE_Tx_Max_Power.dsn: Maximum output power of UE transmitter
- UE_Tx_SpecEmissions.dsn: Spectrum emissions of UE transmitter
- UE_Tx_ACLR.dsn: Adjacent channel leakage(ACLR) of UE transmitter
- UE_Tx_EVM.dsn: Modulation accuracy and phase discontinuity of UE transmitter
- UE_Tx_CCDF.dsn: CCDF of UE transmitter
The HSUPA_RF_Verification_prj project shows on how to build a WTB (Wireless Test Bench) like application with "Summary" data display page.
- HSUPA_UE_Tx_test.dsn: HSUPA Tx WTB include maximum power, adjacent channel leakage power ratio (ACLR), peak code domain error (PCDE), error vector magnitude (EVM).
- 2005A.401 - January 2005 (Initial release, obsoleted by 2005A.402)
Initial release of HSUPA wireless library.
- 2005A.402-July, 2006
- Support FRC2 - FRC7 in Uplink receiver.
- Add HSPA multipath fading channel
- Support both uplink and downlink performance test in fading channel
- Add six new examples for fading channel performance.
- Updated maximum output power measurement
- Create new EVM model to test EVM and phase discontinuity
- Using spec. (2006-3)
- HSUPA_ChDecode was not robust in handling the condition in extreme high SNR
- HSUPA_CHDecode bugs in range checking when the parameter TC_Iteration is out of range
- Rate match is updated to meet the physical channel and spreading factor limitation for each UE category defined in 25.306
- 2008U2.401 - Feb 2009 (enhanced release for HSPA+ Tx for MTK)
- New E-DCH physical category 7
- New FRC 8
- New one-pin EVM measurement function for uplink
- Support setting each E-DCH gain when multiple E-DCHs configured
- 2008U2.402 - March 2009 (enhanced release for HSPA+ Rx for MTK)
- New demodulation performance design for FRC 8 with 4PAM for uplink