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Wireline Applications

The Wireline Applications Guide is available from the ADS installation CD under the Application Guide category. Once installed, it is accessed from the schematic window under the "DesignGuide" menu.


The objective of Wireline Applications is to demonstrate the capability of Advanced Design System to simulate high datarate circuits. The Wireline Applications are categorized into Analog Component and Test, Digital Component and Test, NoiseJitter, and Signal Integrity Simulations.

Analog Component and Test


  1. "Photodiode equivalent circuit "acts as a current source. The equivalent circuit uses a Voltage controlled currentsource to generate an output current waveform. This model can be used to find theperformance of a Transimpedance Amplifier.
  2. "1.25 Gbps CMOS Transimpedance Amplifier Linear Simulation" demonstrates a CMOS Transimpedance amplifier simulation in 50 ohms environment. Transimpedance is plotted using a Vout/Iinputcalculation.
  3. "1.25 Gbps CMOS Transimpedance Amplifier Transient Simulation" shows time domain simulation of CMOS TransimpedanceAmplifier with input current waveform generated through photodiode model. Input current, output voltage waveform and eyediagram at the output is plotted.
  4. "10 Gbps HBT Transimpedance Amplifier Linear Simulation" shows AC simulation of Trans- impedance Amplifier. The inputsignal is a current waveform and the output is a voltage waveform. The Transimpedance performance of this amplifier isplotted.
  5. "10 Gbps Laser Driver Simulation" shows time domain response of a laser driver circuit. The Laser driver is designedusing two stages consisting of Laser driver preamplifier and Travelling wave amplifier to achieve 6 Vpp output. Thesimulation demonstrates flexibility to define differential source with or without jitter. For comparison, the output eyediagram is shown for both cases.
  6. "1 Gbps CMOS VCSEL Laser Driver Circuit Simulation" shows the transient simulation of VCSEL driver with simplifiedVCSEL model. Current waveform and eye diagram is plotted at the output of VCSELequivalent Circuit.
  7. "Large Signal Loop Gain of Ring Oscillator" demonstrates loop gain measurement using S4P equation component. HarmonicBalance Simulation is performed to calculate Loop Gain and phase response of ringoscillator.
  8. "Ring Oscillator Loop Optimization" shows the set up to Optimize Oscillator loop gain and phase response at therequired frequency.
  9. "Ring Oscillator Initial Guess Simulation" demonstrates the creation of initial guess file using transient simulation.This file can be used as initial guess solution to perform Time Assisted HarmonicBalance Simulation.
  10. "Ring Oscillator Time Assisted Harmonic Balance Simulation" shows time assisted harmonic balance simulation of RingOscillator. The initial Guess file generated in previous step is used to reduce simulation time and to avoid convergenceproblems.

Digital Component and Test


  1. "Data buffer", "10 Gbps HBT Clock Buffer", "10 Gbps HBT Divide by 2", "10Gbps HBT Divider Buffer" , "10 Gbps HBT Output Amplifier" , "10 Gbps HBT Latch"and "10 Gbps 2:1 Selector" provides some samples of sub components used indesigning Multiplexer and De-Multiplexer circuits.
  2. "Test_Latch" demonstrates time domain simulation of High Speed Latch usingdifferential signal source.
  3. "2:1 Selector Simulation" shows basic Multiplexer building block simulation.Two differential data sources with different delay parameters are used as inputsignal. The output waveform demonstrates multiplexing action on two inputwaveforms.
  4. "Clock Distribution Simulation" provides time domain simulation of Clockdistribution circuit for 16:1 Multiplexer. The Clock distribution circuit dividesa 10 GHz input frequency to generate 5 GHz, 2.5 GHz, 1.25 GHz and 625 MHz clocksignal. The data display shows the input and divided output waveforms.
  5. "16:1 Multiplexer with Clock Distribution Circuit " demonstrates time domainsimulation of 16:1 Multiplexer for 10 GB application. Frequency domain models ofMicrostrip line, behavioral model for RF System Amplifier and S-Parameter blockare connected at the output of Multiplexer to demonstrate time domain simulationcapability of frequency domain models.
  6. "1:16 De-Multiplexer Simulation With Clock Distribution Circuit" shows timedomain simulation of 1:16 De-Multiplexer for 10 Gbps input signal. TheDe-Multiplexer is designed using a modular approach, consisting of 1:2De-Multipexer and clock distribution circuits.
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