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Documentation:   ADS 2009 Update 1   >  Examples   >  Application Examples   >  A-to-D D-to-A Applications Guide

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A-to-D D-to-A Applications Guide

The Analog-to-Digital Converters Application Guide is available from the ADS installation CD under the Application Guide category.


The objective of the A-to-D D-to-A Applications guide is to demonstrate thecapability of Advanced Design System to design Analog to Digital and Digital toAnalog converters.

The DUT blocks used in this application guide can be replaced with circuitblocks for simulation after making some simulation setup and parameter adjustmentto support the replacing DUT.

Figure 1: Clocked ADC Schematic

ADC Tests

In these series of test templates, ADCs can be fully characterized. Two typesof ADC models are used: with clock and without clock. Those without a clock usethe simulator time step to sample the input analog. ADCs can be fullycharacterized with the following tests.

  • "Test_ADC_with_clock_DNL.dsn" and "Test_ADC_without_clock_DNL.dsn" testDifferential Non Linearity (DNL)
  • "Test_ADC_with_clock_INL.dsn" and "Test_ADC_without_clock_INL.dsn" testIntegral Non linearity (INL)
  • "Test_ADC_with_clock_SNR.dsn" and "Test_ADC_without_clock_SNR.dsn" test Signalto Noise Ratio (SNR)
  • "Test_ADC_with_clock_SINAD.dsn" and "Test_ADC_without_clock_SINAD.dsn" testSignal Noise and Distortion (SINAD)
  • "Test_ADC_without_clock_OffsetError.dsn" tests Offset Error
  • "Test_ADC_without_clock_Gain Error.dsn" tests Gain Error
  • "Test_ADC_without_clock_THD.dsn" tests Total Harmonic Distortion (THD)
  • "Test_ADC_without_clock_SFDR.dsn" tests Spurious-free Dynamic Range(SFDR)
  • "Test_ADC_without_clock_IMD.dsn" tests Intermodulation Distortion (IMD)

Figure 2: SINAD Test for 8-Bit ADC with Clock

ADC Examples

The following ADC examples are included:

  • "ADC_with_clock_Demo" is an example using a clock. It demonstrates a sinusoidal signal input to an 8-bit A-D. The output of the A-D isreconstructed with an ideal Ptolemy D-A and Lowpass filter, and can beobserved with a TK plot. The data display also shows the output of the ADCusing the TimedSink data collector.
  • "ADC_without_clock_Demo" is an example without a clock. It demonstrates a sinusoidal signal input to an 8-bit A-D. The output of the A-D is branchedinto two paths. The first path goes through an ideal Ptolemy D-A toreconstruct the digitized signal back to analog and observe it with TK plot.The second path is used to analyze the output bits. The data display showseach bit and their combinations that make up numerical "words".
  • "Adc_MOS_4bits_Cosim" is an example of a 4-bit ADC.
  • "sub_8Bit_ADC_pipeline" is an example of an 8-bit pipelined MOS ADC.
  • "Test_8Bit_Pipelined_ADC_DNL" is an example of a DNL test for the 8-bitpipelined MOS ADC.
  • "EDGE_8PSKMod_fxfir" is an application example using EDGE modulation.

Figure 3: 8-Bit Pipelined MOS ADC.

DAC Tests

In these series of test templates, DACs can be fully characterized with thefollowing tests.

  • "Test_DAC_without_clock_DNL.dsn" tests Differential Non Linearity (DNL)
  • "Test_DAC_without_clock_SNR.dsn" tests Signal to Noise Ratio (SNR)
  • "Test_DAC_without_clock_SINAD.dsn" tests Signal Noise and Distortion(SINAD)
  • "Test_DAC_without_clock_OffsetError.dsn" tests Offset Error
  • "Test_DAC_without_clock_GainError.dsn" tests Gain Error
  • "Test_DAC_without_clock_THD.dsn" tests Total Harmonic Distortion (THD)
  • "Test_DAC_without_clock_SFDR.dsn" tests Spurious-free Dynamic Range(SFDR)

Figure 4: Gain Error for 8-Bit DAC.

DAC Examples

One general purpose DAC example ("DA_without_clock_cosim") is used to obtainthe input/output characteristics.

Figure 5: DAC Cosimulation Schematic


This guide includes 13 system level logic components that can be used in systemlevel ADC/DAC designs, and 7 MOSFET logic devices for demonstration. These components also have equivalent test circuits and data display setups.

Figure 6: 4-Bit Parallel to Serial Converter.


  • "sub_nonclock_ADC" uses TSTEP, the simulation time step, instead of a clockfor sampling. 1/TSTEP is the sampling rate. It also defines the Bandwidth afterthe FFT process.
  • "sub_clocked_ADC" uses an external clock for sampling. If the aperture erroris not critical, use the non clock ADC for faster simulation.
    sub_nonclock_ADC" and "sub_clocked_ADC"Parameters
    NBITS Number of Bits (up upped1).
    Offset Offset error of the ADC (in Volts).
    Gain Gain error of the ADC (in Volts).
    DNLabs Absolute differential non linearity error of the ADC (in Volts or LSBrange from 0 to 0.7, for example 0.3*LSB). It modifies the output step width to1LSB +/- DNLabs. If DNLabs exceeds 0.7LSB, the model can become nonmonotonic, andcan miss codes.
    FSR Full Scale Range of the ADC (in Volts).
    Vref Minimum value of the Analog input for the ADC.
    InputLevel Magnitude of the fundamental of the analog input spectrum. It normalizesthe coefficients in the polynomial that characterizes the output vs. the input.
    LevelH1 Magnitude of the fundamental at the output with InputLevel as stimulus (inVolts).
    LevelH2(H3, H4, and H5) Magnitude of the second, third, fourth, and fifth Harmonic at the outputwith InputLevel as stimulus (in Volts).
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