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WCDMA3G_SlotTiming


Description: Timing of slot
Library: 3GPPFDD 10-99, Common Physical Channels
Class: SDFWCDMA3G_SlotTiming

Parameters

Name

Description

Default

Sym

Type

Range

ChipRate

chip rate of the system: Chip Rate 3.84M

Chip Rate 3.84M

 

enum

 

SampleRate

number of samples per chip

4

R

int

[1, 32]

NumberOfSlot

number of slots for statistics

15

N

int

[2, 500]

Pin Inputs

Pin

Name

Description

Signal Type

1

in

received signal

complex

2

PSCode

primary synchronization code

int

Pin Outputs

Pin

Name

Description

Signal Type

3

Slot_T

primary CCPCH slot synchronization timing indicator

int

Notes/Equations
  1. This model is used to search the timing of slot.
    Each firing, one token of Slot_T is produced when N × R × 2560 tokens of in and 256 tokens of PSCode are consumed.
  2. Primary synchronization code (PSC code) is unique in the entire system. It is transmitted with the secondary synchronization code during the first 256 chips of each slot of primary CCPCH; primary CCPCH is not transmitted in this period. So the starting position of PSC code in the received signal is the indicator of slot synchronization timing of primary CCPCH.
    Slot timing is implemented by calculating the cross-correlation between the received signal in [ j ] and the PSC code PSCCode [ j ]. Input data is downsampled according to R. The cross-correlation of a complex-valued signal and a real-valued sequence is defined as:

    This equation can be implemented using a structure of tapped delay line illustrated in
    the following figure. P denotes the scope of correlation calculation. PSCode is repeated with the period of 256 tokens.

    Correlator Structure

References
  1. 3GPP Technical Specification TS 25.211 V3.0.0, "Physical Channels and Mapping of Transport Channels onto Physical Channels (FDD)," October 1999.
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