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WCDMA3G Signal Source Design Examples

Introduction

The WCDMA3G_SignalSource_prj project demonstrates the use of base station and user equipment signal source models and EVM measurement models. Two ESG interface demonstrations and an example of ESG Option 100 signal source and 89600 VSA are included. These example designs are described in the following sections:

  • Downlink Test Model 1 Signal Source: 3GPPFDD_BS_Tx_TestModel1.dsn
  • Uplink 12.2 kbps Signal Source: 3GPPFDD_UE_Tx_12_2.dsn
  • ESG Option 100 Compliant Signal Source Demo: 3GPPFDD_ESG100_Demo.dsn
  • EVM Measurement with Non-Synchronized Signal: 3GPPFDD_EVM_Demo.dsn
  • EVM Measurement with Synchronized Signal: 3GPPFDD_EVM_Synch_Demo.dsn
  • ESG E4438C interface demo: 3GPPFDD_ESG4438C.dsn
  • ESG E443xB interface demo: 3GPPFDD_ESG443xB.dsn

Variables used in these designs are listed in the following table.

VAR Parameters12

Parameter Name

Description

Default Value

SamplePerChip

Samples per chip

8

ChipsPerSlot

Chips per slot

2560

NumSlotMeasured

Number of slots to be measured

Depends

StartSlot

The first slot to be measured

0

TimeStart

Start point for timed measurement

(1+StartSlot) × 667e-6

TimeStep

Time step

1/(3840000 × SamplesPerChip)

TimeStop

Stop point for timed measurement

(1+StartSlot+NumSlotMeasured) × 667e-6

FilterLength

Filter length in terms of samples

16 × SamplesPerChip

IF_Freq

IF frequency

190 (MHz)

RF_Freq

RF frequency

2140 (MHz)

RF_BW

RF bandwidth for

50 (MHz)

SignalPower

Signal power

Depends

Downlink Test Model 1 Signal Source

3GPPFDD_BS_Tx_TestModel1.dsn Design

Description

This design generates a file-based signal of downlink test model 1, which can be used as signal source in other designs. The schematic is shown in the following figure.

3GPPFDD_BS_Tx_TestModel1.dsn Schematic

Simulation Results

Simulation results saved in Ref_3GPPFDD_BS_TestM1_I_Data.tim and Ref_3GPPFDD_BS_TestM1_Q_Data.tim are used in the BS_Tx_SpurEmissions.dsn of WCDMA3G_BS_Tx_prj. The spectrum is shown in the following figure.

Spectrum of Transmitted Signal

Benchmark
  • Hardware Platform: Pentium III 450 MHz, 512 MB memory
  • Software Platform: Windows NT 4.0 Workstation, ADS 2002
  • Simulation Time: approximately 1 minute

Uplink 12.2 kbps Signal Source

3GPPFDD_UE_Tx_12_2.dsn Design

Description

This design generates a file-based signal of uplink 12.2 kbps source, which can be used as signal source in other designs. The schematic is shown in the following figure.

3GPPFDD_UE_Tx_12_2.dsn Schematic

Simulation Results

Simulation results are saved in Ref_3GPPFDD_UE_12_2_I_Data.tim and Ref_3GPPFDD_UE_12_2_Q_Data.tim. The spectrum is shown in the following figure.

Spectrum of Transmitted Signal

Benchmark
  • Hardware Platform: Pentium III 450 MHz, 512MB memory
  • Software Platform: Windows NT 4.0 Workstation, ADS 2002
  • Simulation Time: approximately 1 minute

ESG Option 100 Compliant Signal Source Demo

3GPPFDD_ESG100_Demo.dsn Design

Features
  • ESG option 100 compliant signal source
  • VSA 89600 measurement

Description

This design demonstrates how the use of an ESG 100 compliant signal source in the 3GPPFDD design library and the VSA 89600 measurement model. The schematic is shown in the following figure.

3GPPFDD_ESG100_Demo.dsn Schematic

The baseband signal source data is generated by the 3GPPFDD_UpLk model. It is set as one DPCCH plus six DPDCHs.

The VSA89600_1 model will call Agilent 89600 vector signal analyzer, which requires Glacier to be installed. The Glacier file setting is 3GPPFDD_ESG100_Demo.set; it measures spectrum, code domain power and constellation.

Simulation Results

The VSA results are shown in the following figure.

89600 VSA results

Benchmark
  • Hardware Platform: Pentium III 450 MHz, 512MB memory
  • Software Platform: Windows NT 4.0 Workstation, ADS 2002

EVM Measurement with Non-synchronized Signal

3GPPFDD_EVM_Demo.dsn Design

Description

This design demonstrates the 3GPP EVM measurement. The schematic is shown in the following figure.

The measurement can be performed on specified slots. The test and reference signals are automatically aligned at the slot boundary. If the test signal is severely contaminated, it is difficult to align it to the slot boundary and an incorrect EVM value could be obtained; therefore, the test and reference signals should be aligned outside the EVM measurement model as described in the EVM measurement example 3GPPFDD_EVM_Synch_Demo.dsn in the next section.

A recommended method to synchronize the test and reference signal is to test the EVM at different offsets between the signals. The hypothesis is the minimum value will be obtained if the reference and test signal are aligned.

3GPPFDD_EVM_Demo.dsn Schematic

Simulation Results

Simulation results are displayed in 3GPPFDD_EVM_Demo.dds. EVM is preset at 1.23%, the simulation results of two slots are 1.212197% and 1.249422%.

Benchmark
  • Hardware Platform: Pentium III 450 MHz, 512MB memory
  • Software Platform: Windows NT 4.0 Workstation, ADS 2002
  • Data Points: 2 slots
  • Simulation Time: 50 seconds

EVM Measurement with Synchronized Signal

3GPPFDD_EVM_Synch_Demo.dsn Design

Description

This example demonstrates how to measure EVM between synchronized test and reference signals. The schematic is shown in the following figure.

The EVM measurement model is hidden inside the EVM measurement subnetworks. The source is a standard QPSK signal. The test and reference signals are synchronized with each other to achieve high measurement accuracy. The two Tk plot models can be activated to view the difference between the reference and test signals.

3GPPFDD_EVM_Synch_Demo.dsn Schematic

Simulation Results

Simulation results are displayed in 3GPPFDD_EVM_Synch_Demo.dds. EVM is preset at 12%, the simulation results of 3 slots are 11.990%, 11.993% and 12.081%.

Benchmark
  • Hardware Platform: Pentium III 450 MHz, 512 MB memory
  • Software Platform: Windows NT 4.0 Workstation, ADS 2002
  • Data Points: 3 slots
  • Simulation Time: 22 seconds

ESG 4438C Interface Demo

3GPPFDD_ESG4438C.dsn Design

Description

This design demonstrates how a ESG4438C instrument interface model is used with 3GPP source model.

The schematic is shown in the following figure.

3GPPFDD_ESG4438C.dsn Schematic

Benchmark
  • Hardware Platform: Pentium III 450 MHz, 512 MB memory
  • Software Platform: Windows NT 4.0 Workstation, ADS 2002

ESG 443xB Interface Demo

3GPPFDD_ESG443xB.dsn Design

Description

This design demonstrates how a ESG443xB instrument interface model is used with 3GPP source model.

The schematic is shown in the following figure

3GPPFDD_ESG443xB.dsn Schematic

Benchmark
  • Hardware Platform: Pentium III 450 MHz, 512 MB memory
  • Software Platform: Windows NT 4.0 Workstation, ADS 2002
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