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WCDMA3G_FirstIntlvr


Description: First interleaver
Library: 3GPPFDD 10-99, Channel Coding
Class: SDFWCDMA3G_FirstIntlvr

Parameters

Name Description Default Sym Type Range
LinkDir link direction: Downlink, Uplink Downlink   enum  
TrCHType transport channel type(used in uplink only): DCH_8_kbps, DCH_16_kbps, DCH_32_kbps, DCH_64_kbps, DCH_128_kbps, DCH_256_kbps, DCH_512_kbps, DMCH_2_4_kbps, DMCH_12_2_kbps, DMCH_64_kbps, DMCH_144_kbps, DMCH_384_kbps, DMCH_2048_kbps DCH_8_kbps   enum  
TTI transmission time interval: TTI_10ms, TTI_20ms, TTI_40ms, TTI_80ms TTI_10ms   enum  
DL_PhyCHType downlink physical channel type: DPCH_15kbps_TF0_T2_P4, DPCH_15kbps_TF2_T2_P4, DPCH_30kbps_TF0_T2_P2, DPCH_30kbps_TF2_T2_P2, DPCH_30kbps_TF0_T2_P4, DPCH_30kbps_TF2_T2_P4, DPCH_30kbps_TF0_T2_P8, DPCH_30kbps_TF2_T2_P8, DPCH_60kbps_TF0_T2_P4, DPCH_60kbps_TF2_T2_P4, DPCH_60kbps_TF0_T2_P8, DPCH_60kbps_TF2_T2_P8, DPCH_120kbps_TF8_T4_P8, DPCH_120kbps_TF0_T4_P8, DPCH_240kbps_TF8_T4_P8, DPCH_240kbps_TF0_T4_P8, DPCH_480kbps_TF8_T8_P16, DPCH_480kbps_TF0_T8_P16, DPCH_960kbps_TF8_T8_P16, DPCH_960kbps_TF0_T8_P16, DPCH_1920kbps_TF8_T8_P16, DPCH_1920kbps_TF0_T8_P16, PCCPCH DPCH_30kbps_TF2_T2_P8   enum †
PhyCHNum physical channel number 1 N d int [1, ∞)
† where
TF n = number of transmit format indicator bits
T n = number of transmit power control bits
P n = number of pilot bits
F n = number of feedback indicator bits

Pin Inputs

Pin

Name

Description

Signal Type

1

In

input data

int

2

inSize

input data length

int

Pin Outputs

Pin

Name

Description

Signal Type

3

Out

ouput data after interleaving

int

4

outSize

output data length

int

Notes/Equations
  1. This model is used for first interleaving. First interleaving is a block interleaver with inter-column permutations after rate matching in a downlink or radio frame equalization in an uplink.
    In a downlink, M × Nd × NTTI tokens of Out and one token of outSize are produced when M × Nd × NTTI tokens of pin In and one token of inSize are consumed, where NTTI equals 1, 2, 4, or 8 when TTI is set to 10 ms, 20 ms, 40 ms, or 80 ms, respectively. Refer to the following table for the value of M.
    Downlink M Values

    DL_PhyCHType

    M=PhyCH Interleaving Block Length (Bits)

    DPCH_15kbps_TF0_T2_P4

    60

    DPCH_15kbps_TF2_T2_P4

    30

    DPCH_30kbps_TF0_T2_P2

    240

    DPCH_30kbps_TF2_T2_P2

    210

    DPCH_30kbps_TF0_T2_P4

    210

    DPCH_30kbps_TF2_T2_P4

    180

    DPCH_30kbps_TF0_T2_P8

    150

    DPCH_30kbps_TF2_T2_P8

    120

    DPCH_60kbps_TF0_T2_P4

    510

    DPCH_60kbps_TF2_T2_P4

    480

    DPCH_60kbps_TF0_T2_P8

    450

    DPCH_60kbps_TF2_T2_P8

    420

    DPCH_120kbps_TF8_T4_P8

    900

    DPCH_120kbps_TF0_T4_P8

    900

    DPCH_240kbps_TF8_T4_P8

    2100

    DPCH_240kbps_TF0_T4_P8

    2100

    DPCH_480kbps_TF8_T8_P16

    4320

    DPCH_480kbps_TF0_T8_P16

    4320

    DPCH_960kbps_TF8_T8_P16

    9120

    DPCH_960kbps_TF0_T8_P16

    9120

    DPCH_1920kbps_TF8_T8_P16

    18720

    DPCH_1920kbps_TF0_T8_P16

    18720

    PCCPCH

    270
    In an uplink, M tokens of Out and one token of outSize are produced when M tokens of pin In and one token of pin inSize are consumed. Refer to the following table for the value of M.
    Uplink M Values
    TrCHType M=TrCH Interleaving Block Length (Bits)
    TTI=10 ms TTI=20 ms TTI=40 ms TTI=80 ms
    DCH_8_kpbs 312 552 1032 2016
    DCH_16_kpbs 552 1032 2016 3960
    DCH_32_kbps 1032 2016 3960 7888
    DCH_64_kbps 1980 3900 7740 15432
    DCH_128_kbps 3900 7740 15432 30808
    DCH_256_kbps 7740 15432 30808 61560
    DCH_512_kbps 15432 30808 61560 123040
    DMCH_2_4_kbps     360  
    DMCH_12_2_kbps   804    
    DMCH_64_kbps   3900    
    DMCH_144_kbps   8700    
    DMCH_384_kbps   23112    
    DMCH_2048_kbps   123040    
  2. Model functions
    Input bits and data length are loaded from the input buffer. The input bits from the beginning to the input data length are valid data for the first interleaving and are denoted as xi1, xi2, ..., xiXi, where i is the TrCH number and Xi is the number of bits (at this stage Xi is assumed and guaranteed to be an integer multiple of TTI).
    The number of columns Ci are selected (see the following table).
    Permutation Patterns for First Interleaving

    TTI

    Number of Ci Columns

    Inter-column Permutation Patterns

    10 ms

    1

    {0}

    20 ms

    2

    {0,1}

    40 ms

    4

    {0,2,1,3}

    80 ms

    8

    {0,4,2,6,1,5,3,7}
    The number of rows (Ri) are determined.
    Ri = Xi / Ci
    Input bit sequence is placed into the Ri x Ci rectangular matrix row-by-row starting with bit xi1 in the first column of the first row and ending with bit xi,(Ri,Ci) in column Ci of row Ri:

    Inter-column permutation is performed based on the pattern {P1(j)} (j=0,1, ..., Ci -1) shown in the previous table, where P1(j) is the original column position of the j th permuted column. After permutation f columns, bits are denoted by yik:

    Output bit sequence yik of the first interleaving is read column-by-column from the inter-column permuted Ri x Ci matrix. Bit yi,1 corresponds to the first row of the first column and bit yi,(RiCi) corresponds to row of column Ci.
    Data is output after interleaving and pad all zero if the valid length is smaller than the buffer size, the value of outSize is output equal to inSize.

References
  1. 3GPP Technical Specification TS25.212 V3.0.0, "Multiplexing and Channel Coding (FDD)," October 1999.
  2. 3GPP Technical Specification TS25.101 V3.0.0, "UE Radio Transmission and Reception (FDD)," October 1999.
  3. 3GPP Technical Specification TS25.104 V3.0.0, "UTRA(BS) FDD: Transmission and Reception," October 1999.
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