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WCDMA3G_DnLkScrambler


Description: Downlink scrambling code generator
Library: 3GPPFDD 10-99, Spreading & Modulation
Class: SDFWCDMA3G_DnLkScrambler

Parameters

Name

Description

Default

Type

Range

ChipRate

chip rate of the system: Chip Rate 3.84M

Chip Rate 3.84M

enum

 

CodeType

type of scrambling codes: Primary, Secondary

Primary

enum

 

P_index

index of primary code

1

int

[0, 511]

S_index

index of secondary code

0

int

[0, 15]

Pin Outputs

Pin

Name

Description

Signal Type

1

out

scrambling code sequence

complex

2

INDEX

scrambling code index

int

Notes/Equations
  1. This model is used to generate scrambling code for downlink transmission. The index of this sequence is also conveyed. Each firing, a cycle of tokens is produced in out, one is produced in INDEX . Scrambling code sequences are constructed by combining two real sequences into a complex sequence. Each of the two real sequences are constructed as the position-wise modulo-2 sum of 38400 chip segments of two binary m-sequences generated by two 18-degree generator polynomials. The cycle of the scrambling code is 38400.
  2. If CodeType = Primary, set S_index to 0; if CodeType = Secondary, set S_index > 0.
  3. The scrambling codes index = 0,1, ..., 8191 are divided into 512 sets each of a primary scrambling code and 15 secondary scrambling codes. There is one-to-one mapping between each primary scrambling code and 15 secondary scrambling codes in a set such that i th primary scrambling code corresponds to i th set of scrambling codes. Each cell is allocated one primary scrambling code. The primary CCPCH is always transmitted using the primary scrambling code. The other downlink physical channels can be transmitted with either the primary or a secondary scrambling code from the set associated with the primary scrambling code of the cell.
    Index = 16 × P_index + S_index, where P_index is the number of the set of scrambling code. If S_index = 0, the output scrambling code is a primary code; If S_index is a number in [1, 15], the output scrambling code is a secondary code that belongs to the set of scrambling code determined by P_index.
  4. The configuration of sequence generator is shown in the following figure. The x sequence is constructed using polynomials x18 + x7 + 1; the y sequence is constructed using x18 + x10 + x7 + x5 + 1. The initial values:

    x(0) = − 1, x(1) = x(2) = ... = x(16) = x(17) = 1
    y(0) = y(1) = ... y(160 = y(17) = −1

    The out from x sequence after it is shifted by number index is summed with the out from y sequence. The resulting sequence is position-wise modulo-2 sum of 38400 chips. The sequence phase is shifted by 131072 between I and Q sequence. I and Q are then combined into a complex sequence as the downlink scrambling code at the out port.

    Downlink Scrambling Code Generator

References
  1. 3GPP Technical Specification, TS 25.213, V3.0.0, "Spreading and modulation (FDD)," October 1999.
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