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WCDMA3G Base Station Transmitter Design Examples

Introduction

The WCDMA3G_BS_Tx_prj project shows base station transmitter measurement characteristics including maximum output power, occupied bandwidth, complementary cumulative distribution function (CCDF), spectrum emission, spurious emission, adjacent channel leakage power ratio (ACLR) and peak code domain error and code domain power. The downlink frequency band is set at 2110 to 2170 MHz and the signal sources are the test models defined in 25.141.

Designs for these measurements include:

  • Maximum power measurements: BS_Tx_MaxPower.dsn
  • Occupied bandwidth measurements: BS_Tx_Occupied_BW.dsn
  • Complementary cumulative distribution function measurements: BS_Tx_CCDF.dsn
  • Transmitter spectrum emissions measurements: BS_Tx_Spec_Emission.dsn
  • Adjacent channel leakage power measurements in frequency domain: BS_Tx_ACLR.dsn
  • Transmitter EVM measurements: BS_Tx_EVM.dsn
  • Transmitter peak code domain error measurements: BS_Tx_Pk_Code_Error.dsn
  • Signal power distribution measurements in code domain: BS_Tx_Code_Domain_Power.dsn
  • Spurious emission measurement: Bs_Tx_SpurEmission.dsn

In the basic structure of the example designs a downlink signal source model generates an RF signal and a measurement model implements the measurements.

Simulation results are displayed in data display files, which carry the same names as the designs.

The downlink signal source 3GPPFDD_RF_Downlink supports fourteen types of sources, including four data rate fully coded sources and three types of test model 1, test model 2, two types of test model 3 and test model 4 and three types of test model 5. Type is based on the SourceType parameter. The hierarchical schematic of 3GPPFDD_RF_Downlink is shown in the following figure.

The Fully coded source 3GPPFDD_DL_Source and test models are selected by IfElse model then modulated to RF signal by 3GPPFDD_RF_Mod. A reference signal is output after RRC filtering. For the details regarding the fully-coded signals, refer to 3GPPFDD_DL_Source documentation.

The common variables used in these designs are listed in the following table.

VAR Parameters

Parameter Name

Description

Default Value

SpecVersion

Specification version

2

SamplePerChip

Samples per chip

8

ChipsPerSlot

Chips per slot

2560

NumSlotMeasured

Number of slots to be measured

Depends on measurements

StartSlot

The first slot to be measured

0

TimeStart

Start point for timed measurement

(1 + StartSlot) × 667e-6

TimeStep

Time step

1/(3840000 × SamplesPerChip)

TimeStop

Stop point for timed measurement

(1+ StartSlot + NumSlotMeasured) × 667e-6

FilterLength

Filter length in terms of samples

16

FCarrier

RF frequency

2140 (MHz)

RF_BW

RF bandwidth

50 (MHz)

SignalPower

Signal power

10 (dBm)

Maximum Power Measurements

BS_Tx_MaxPower.dsn design

Features
  • maximum power measurement
  • test model 1 is used as the signal source
  • synchronized slot measurement

Description

BS_Tx_MaxPower.dsn measures the maximum power of downlink signal. Normally, the base station maximum output power must remain within +2 dB and -2 dB of the manufacturer's rated power.

The schematic for this design is shown in the following figure.

BS_Tx_MaxPower.dsn Schematic

3GPPFDD_TestModel1 consists of 16/32/64 DPCH channels, one PICH channel, one primary CPICH channel and one PCCPCH+SCH channel, an SCCPCH is included in version 2002-03. The PICH channel and DPCH channels are transmitted after different time offsets. When OutputMode = Ramp, the output power will reach its preset value after all channels are transmitted. Meaningful maximum power is reached after 15 slots.

Simulation Results

The following figure shows the performance of maximum output power.

Maximum Power Curve

Benchmark
  • Hardware Platform: Pentium 4 2.2 GHz, 512 MB memory
  • Software Platform: Windows 2000, ADS 2003C
  • Data Points: 20 slots
  • Simulation Time: approximately 13 seconds

Occupied Bandwidth Measurements

BS_Tx_OccupiedBW.dsn Design

Features
  • occupied bandwidth measurement
  • test model 1 is used as the signal source
  • synchronized slot measurement

Description

BS_Tx_OccupiedBW.dsn measures the occupied bandwidth of downlink signal. The schematic is shown in the following figure.

Occupied bandwidth is a measure of the bandwidth containing 99% of the integrated power for the transmitted spectrum and is centered on the assigned frequency. The occupied bandwidth must be less than 5 MHz based on a chip rate of 3.84 Mcps.

BS_Tx_OccupiedBW.dsn Schematic

Simulation Results

The signal power density spectrum is obtained using the spectrum analyzer. The following figure shows the signal power density spectrum. A marker is placed to identify the occupied bandwidth.

Occupied Bandwidth Curve

Benchmark
  • Hardware Platform: Pentium 4 2.2 GHz, 512 MB memory
  • Software Platform: Windows 2000, ADS 2003C
  • Data Points: 1 slot
  • Simulation Time: 4 seconds

Complementary Cumulative Distribution Function Measurements

BS_Tx_CCDF.dsn Design

Features
  • CCDF measurement
  • test model 1 is used as the signal source
  • synchronized slot measurement

Description

BS_Tx_CCDF.dsn measures the CCDF of a downlink signal. The schematic is shown in the following figure.

BS_Tx_CCDF.dsn Schematic

Simulation Results

The measurement is deployed on 5 slots of a stable signal after the first frame (15 slots). The following figure shows the CCDF performance.

Base Station Transmitter CCDF Curve

Benchmark
  • Hardware Platform: Pentium 4 2.2 GHz, 512 MB memory
  • Software Platform: Windows 2000, ADS 2003C
  • Data Points: 5 slots
  • Simulation Time: 4 seconds

Transmitter Spectrum Emissions Measurements

BS_Tx_Spec_Emission.dsn Design

Feature
  • Test model 1 is used as the signal source
  • Out-of-band power is measured by sweeping the center frequency of the bandpass filter

Description

BS_Tx_Spec_Emission.dsn measures the base station transmitter spectrum emission. Out-of-band emissions are unwanted emissions immediately outside the channel bandwidth resulting from the modulation process and non-linearity in the transmitter. The following figure shows the schematic for this design.

BS_Tx_Spec_Emission.dsn Schematic

Notes

Emissions must not exceed the maximum level specified by the mask in the frequency range with offset from Δfmin −12.5 MHz to Δfmax 12.5 MHz from the carrier frequency. Mask values are specified in the following table. There are some small differences in different versions[2]. A sweeper is used to simulate all frequency offsets.

Spectrum Emission Mask Values
Frequency Offset Δf Maximum Level Measurement Bandwidth †
Base Station Maximum Output Power P < 31 dBm
2.5 ≤ Δf < 2.7 MHz -22 dBm 30 kHz  
2.7 ≤ Δf < 3.5 MHz -22 - 15(Δf - 2.7) dBm 30 kHz
    30 kHz
3.5 ≤ Δf < 7.5 MHz -21 dBm 1 MHz
7.5 ≤ Δf ≤ Δfmax MHz -25 dBm 1 MHz
Base Station Maximum Output Power 31 ≤ P < 39 dBm
2.5 ≤ Δf < 2.7 MHz P - 53 dBm 30 kHz  
2.7 ≤ Δf < 3.5 MHz P - 53 - 15(Δf - 2.7) dBm 30 kHz
†† P - 65 dBm 30 kHz
3.5 ≤ Δf < 7.5 MHz P - 52 dBm 1 MHz
7.5 ≤ Δf ≤ Δfmax MHz P - 56 dBm 1 MHz
Base Station Maximum Output Power 39 ≤ P < 43 dBm
2.5 ≤ Δf < 2.7 MHz -14 dBm 30 kHz
2.7 ≤ Δf < 3.5 MHz -14 - 15(Δf - 2.7) dBm 30 kHz
†† -26 dBm 30 kHz
3.5 ≤ Δf < 7.5 MHz -13 dBm 1 MHz
7.5 ≤ Δf ≤ Δfmax MHz P - 56 dBm 1 MHz
Base Station Maximum Output Power P ≥ 43 dBm
2.5 ≤ Δf < 2.7 MHz -14 dBm 30 kHz
2.7 ≤ Δf < 3.5 MHz - 14 - 15(Δf - 2.7) dBm 30 kHz
†† -26 dBm 30 kHz
3.5 ≤ Δf ≤ Δfmax MHz -13 dBm 1 MHz
† the first and last measurement positions with a 30 kHz filter are 2.515 and 3.485 MHz, respectively.  the first and last measurement positions with a 2 MHz filter are 4 MHz and (Δfmax - 500 kHz), respectively.
†† This frequency range ensures that the range of values of f_offset is continuous.

Simulation Results

The spectrum emission is stored in the sink after 15 slots. The following figure shows the spectrum emission for the base station output powers and masks listed in the previous table.

Spectrum Emission Curves

Benchmark
  • Hardware Platform: Pentium 4 2.2 GHz, 512 MB memory
  • Software Platform: Windows 2000, ADS 2003C
  • Data Points: 1slot sweeping frequency offset from -12.5 MHz to 12.5 MHz
  • Simulation Time: approximately 20 minutes

Adjacent Channel Leakage Power Measurements in Frequency Domain

BS_Tx_ACLR.dsn Design

Features
  • adjacent channel leakage power ratio measured in the frequency domain
  • test model 1 is used as the signal source
  • synchronized slot measurement

Description

BS_Tx_ACLR.dsn measures the base station transmitter adjacent channel leakage power ratio (ACLR) in the frequency domain. Better ACLR can be obtained using a longer filter length for the RRC filter in the signal source. The parameter FilterLength has a default value of 16; however, increasing this value to 24 or 32 should result in a better ACLR. This may also correlate better to ACLR measurements when using instruments from Agilent Technologies. ACLR is the ratio of the transmitted power to the power measured after a receiver filter in the adjacent channel. In this design, both the transmitted and received power are measured through a root raised-cosine and roll-off 0.22 matched filter; noise power bandwidth is set to 3.84 MHz. The schematic for this design is shown in the following figure.

The de-activated DUT in parallel is an alternate DUT that supports circuit co-simulation that can be replaced with the user's design.

BS_Tx_ACLR.dsn Schematic

Simulation Results

The Spectrum analyzer is used to measure the transmitted power and adjacent channel power in the frequency domain. When the base station adjacent channel offset is +5 or −5 MHz, the ACLR limit is 45 dB; when the base station adjacent channel offset is +10 or −10 MHz, the ACLR limit is 50 dB. The measurement is deployed after the first frame (15 slots) and the signal becomes stable. The following figure shows the ACLR performance of the base station transmitter.

Base Station Transmitter Spectrum and ACLR Performance

Benchmark
  • Hardware Platform: Pentium 4 2.2 GHz, 512 MB memory
  • Software Platform: Windows 2000, ADS 2003C
  • Data Points: 0.1 slot
  • Simulation Time: approximately 23 seconds

Transmitter EVM Measurements

BS_Tx_EVM.dsn Design

Features
  • error vector magnitude measurements
  • test model 4 is used as the signal source
  • synchronized slot measurement with reference signal

Description

This design measures the error vector magnitude (EVM) of the base station transmitter. EVM is the difference between the measured waveform and the theoretical modulated waveform and shows modulation accuracy. EVM expressed as a percentage must not be worse than 17.5%.

The schematic for this design is shown in the following figure.

BS_Tx_EVM.dsn Schematic

3GPPFDD_EVM Schematic

Simulation Results

EVM =0.000123%

Benchmark
  • Hardware Platform: Pentium 4 2.2 GHz, 512 MB memory
  • Software Platform: Windows 2000, ADS 2003C
  • Data Points: 1 slot
  • Simulation Time: approximately 50 seconds

Transmitter Peak Code Domain Error Measurements

BS_Tx_Pk_Code_Error.dsn Design

Features
  • peak code domain error calculation
  • test model 3 is used as the signal source
  • synchronized slot measurement with reference signal

Description

The schematic for this design is shown in the following figure. The code domain error is calculated by projecting the error vector power onto the code domain (that is, each code of the spreading code set). The peak code domain error is defined as the maximum value for the code domain error and cannot exceed −33 dB.

BS_Tx_Pk_Code_Error.dsn Schematic

Simulation Results

The peak code domain error is shown in the following figure.

Peak Code Domain Error of Base Station Transmitter

Benchmark
  • Hardware Platform: Pentium 4 2.2 GHz, 512 MB memory
  • Software Platform: Windows 2000, ADS 2003C
  • Data Points: 1 slot
  • Simulation Time: 50 seconds

Signal Power Distribution Measurements in Code Domain

BS_Tx_Code_Domain_Power.dsn Design

Features
  • code domain power distribution measurement
  • test model 3 is used as the signal source

Description

This design is used to analyze downlink signal power distribution in the code domain. The schematic is shown in the following figure. A fixed-rate signal source is used to generate the baseband signal, pass it through the modulator; an upconverter is used to get the RF signal. The complex envelope of the RF signal is removed to project its power into the code domain.

BS_Tx_Code_Domain_Power.dsn Schematic

The received chip stream can be described as a vector Z of complex valued samples. The vector is of length N = n × m, where n is the number of symbol periods in the measurement interval and m is the spreading factor (m chips per symbol, with one sample per chip). To project Z into the code domain, individual complex valued elements of Z are defined as:

vk where k = 0, 1, ..., N − 1

The chip stream is de-scrambled and divided into symbol vectors,

for s = 0, 1, ..., n − 1

A 2-dimensional matrix is generated of the projections of each received symbol vector onto each code vector Ci ( i = 0 ... m − 1). Ci = ci + jci and ci is the ith spreading code. is its complex conjugate.

By calculating the square of the magnitudes of the terms in Pz we arrive at a matrix of power coefficients that can be further processed by summing the values for each code across all symbols and normalizing to the received signal power. This produces the code domain power coefficient vector

For each code i, we have calculated the projection of a symbol-long segment of the vector V onto code vector Ci for each symbol in the measurement interval. We summed these projected powers over all symbols then normalized to the received signal power.

ρS = { ρ0, ρ1, ..., ρm -1}

The power coefficients vector can be plotted, at least conceptually, as a histogram to give a display the power distribution in the code domain for the vector Z.

Simulation Results

Signal power distribution in the code domain is shown in the following figure. Here OVSF code of layer 8 is used, the range of code index is from 0 to 255.

Signal Power Distribution in Code Domain

Benchmark
  • Hardware Platform: Pentium 4 2.2 GHz, 512 MB memory
  • Software Platform: Windows 2000, ADS 2003C
  • Data Points: 1 slot per code (2560 chips per slot)
  • Simulation Time: approximately 83 seconds

Spurious Emissions Measurements

BS_Tx_SpurEmissions.dsn Design

Features
  • file-based signal source of test model 1
  • circuit co-simulation

Description

Spurious emissions are caused by unwanted transmitter effects such as harmonics emission, parasitic emission, intermodulation and frequency conversion products, but exclude out-of-band emissions. BS_Tx_SpurEmissions.dsn measures harmonics emission using the ADS circuit envelope simulator. The following figure shows the schematic for this design.

BS_Tx_SpurEmissions.dsn Schematic

The timed I, Q source data are generated by WCDMA3G_SignalSource_prj, which measured IF emissions plus third-harmonic emissions of LO. By changing fundamental frequencies and their order, designers can observe different harmonic emissions. The ITU-R Recommendation SM.329-7[1] defined two mandatory categories of limits for spurious emissions according to [2].

Simulation Results

The following figure shows spectrum of signal on carrier frequency.

Main Signal of Base Station Transmitter

The following figure shows spectrum of spurious emissions on IF frequency plus third-order harmonics of LO frequency.

Spurious Emissions of Base Station Transmitter

Benchmark
  • Hardware Platform: Pentium 4 2.2 GHz, 512 MB memory
  • Software Platform: Windows 2000, ADS 2003C
  • Data Points: 5 slots
  • Simulation Time: approximately 1 minute

References

  1. 3GPP Technical Specification TS 34.121 V3.3.0 "Terminal conformance Specification: Radio transmission and reception (FDD)," December 2000.
  2. 3GPP Technical Specification TS 25.104 V3.5.0, "UTRA(BS) FDD: Radio transmission and Reception," December 2000.
  3. 3GPP Technical Specification TS 25.141 V3.4.1, "Base station conformance test," December 2000.
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