S-Parameter Test Labs and Sequencer

S-parameter test labs and Sequencer both enable you to take multiple simulations and combine them into one simulation run. An S-parameter test lab enables you to calculate the S-parameters of multiple N-port networks in a single simulation run. A Sequencer controller enables you to sequence multiple simulations into a single simulation run.

An S-parameter test lab is a schematic that contains one S-parameter test lab component and one or more test benches. A test bench is a schematic that contains an N-port network and terminations for each port of the network. In multiple stage circuit design practices, the designer is interested in viewing the inter-stage circuit behavior of all stages simultaneously. In particular, it is desired for each stage to be terminated not in 50 ohms, but in the applicable input/output impedances of adjacent stages. See RefNets for more information on using RefNets in conjunction with the S-parameter test lab feature.

There are many reasons why you may want to combine test benches into sequence, using a Sequencer controller. These include optimizing a variable across multiple simulations, enabling complex instrument control in Ptolemy and running a series of verifications tests on a design. To sequence these simulations, you will need to create a test bench that includes all the desired simulation controllers and the top-level design file.

Comparison of Test Lab and Sequencer

Creating a Test Bench

Port component

To create a test bench you should declare your schematic (to be tested) as a parametric subnetwork. As with any parameter subnetwork, you can add parameters and set the library location. To learn how to create a parameter subnetwork see Creating a Parametric Subnetwork.

Unlike parametric subnetworks, a test bench schematic should not have any Port components. Instead, it should be terminated with proper terminations, power sources with built-in resistors, or RefNet component.

Supported terminal components for S-parameter test lab

Although optional, you should set your symbol for the new subnetwork to be SYM_TestBench:

To set this symbol, select File > Design Parameters... and change the symbol name to SYM_TestBench as shown in the following figure:

S-Parameter Test Labs

Test Lab Usage Rules

1. As its name implies, the S-parameter test lab is dedicated to S-parameter simulation. As such, a nonlinear design will be linearized about its DC operating point.
2. The S-parameter test lab simulation will ignore any simulation controllers contained in a test bench. It is still useful to have test bench controllers because they can be used to perform a stand-alone simulation of the test bench.
3. The S-parameter test lab should not contain any circuit components other than test benches. Any connectivity (wires) in the S-parameter test lab is ignored. Any component in the S-parameter test lab that has one or more pins is ignored.
4. The minimum requirements for an S-parameter test lab to function are:
   • At least one test bench
   • One S_ParamTestLab Simulation Controller
5. By convention, S-parameter test lab names should end in _TL . This is not required.
6. Only one S-parameter test lab simulation controller is allowed. A SweepPlan can be used to specify multiple continuous or discontinuous frequency combs.
7. S-parameter test labs support the following auxiliary simulation controllers: Options Plan, Sweep Plan, Parameter Sweep, Optimization, Statistical, and DOE controllers.
8. Variable equations (simulator expressions) and measurement expressions are supported. As with any top-level design, variables defined at the top are recognized throughout the hierarchy.
9. Tuning is supported in the S-parameter test lab. Tuning within an S-parameter test lab works identically to tuning for a normal top-level design. Users can push into a test bench and select parameters or variables to tune. Users can also tune variables and item parameters in the schematic window that displays the S-parameter test lab.
10. Global nodes are supported, but they are not global across test benches. They are global within each test bench.
11. Any global expression found in a test bench is available to all other test benches.
12. The S_ParamTestLab controller has virtually the same user interface and displayed parameters as the standard S-Parameter controller.

Configuring an S-Parameter Test Lab

1. Determine the design files for which you want to calculate the S-parameters. You will create a test bench for each of these designs.
2. Create the S-Parameter Test Lab.
   • Create a new schematic. This will be the test lab. It is recommended (but not required) that the name of the test lab schematic end in _TL . For this example, the name My_testlab_TL is used.
     
     

     Schematic window with design named using _TL S-parameter test lab naming convention

   • In the S-parameter test lab schematic, change to the Simulation-S_Param palette. Place an S_ParamTestLab controller (icon appears as SP Lab ). Configure the S-parameter test lab controller the same way you would configure a standard S-parameter analysis.
     
     

     Test Lab S-parameter controller icon, SP Lab.

   • In the S-parameter test lab schematic, place the test bench, My_testbench1_TB , created earlier. For illustration purposes, assume that test benches My_testbench2_TB and My_testbench3_TB were also created. These are placed into the completed test lab.
     
     

     Completed S-parameter test lab

Notes

1. Both the Sequencer and S-parameter test lab calculate measurement equations that are contained in a test bench. The measurement equation is calculated only for the test bench that contains it. The measurement equation should not use the test bench instance id to refer to data (for example, S-parameters) that is generated for the test bench.
2. If only one test bench is placed, the testbenchID prefix may be omitted. However, this is not recommended.

Data Display Naming Convention for Simulation Results

Standard Results Data

Standard S-parameter simulation output with Noise turned on produces the following standard output to the dataset:

S, S(i,j)
PortZ, PortZ(1), PortZ(2), PortZ(n), freq
Icor, Icor(i,j)
nf, nf(i), Nfmin
Rn, Sopt, te, te(n)

Where i = 1,2,... and j = 1,2,... are port indices.

An S-parameter test lab controller will also calculate these items. However, the test bench Instance ID will prefix the names. For example, an S-parameter test lab containing two, two-port test benches will produce the following results:

X1.S(1,1)
X1.S(2,1)
X1.S(1,2)
X1.S(2,2)
X2.S(1,1)
X2.S(2,1)
X2.S(1,2)
X2.S(2,2)

where X1 and X2 are the test bench instance ID names appearing in the test lab. If only one test bench appears in the S-parameter test lab, then the test bench prefix is not required.

Measurement Equation Results Data

Measurement equations appearing in the S-parameter test lab appear in the dataset as

MeasurementEquationName1
MeasurementEquationName2

Measurement equations appearing in test benches in an S-parameter test lab will also appear in the dataset as

MeasurementEquationName1
MeasurementEquationName2
...

However, if the same measurement equation name appears in the S-parameter test lab and a participating test bench, the following nomenclature is used

_Testlab1_TL_sp.MeasurementEquationName1
TestBench1_TB.MeasurementEquationName1

Optimization and Statistical Analysis

Configuring optimization and statistical analyses in an S-parameter test lab is similar to configuring them for a standard S-parameter analysis. An example project, TestLab_HOWTO_prj , is available in the ADS examples directory, $HPEESOF_DIR/examples/Tutorial .

This example illustrates optimization in an S-parameter test lab. The reader is advised to review the example's Readme.dsn file, which contains detailed information.

Sequencer

Creating a Sequence

Create a test bench, then you are ready to specify the sequence. To do so, you'll need to create a new top-level design and instantiate each test bench in it. Next, you'll need to add a Sequencer controller. This controller is available on the Simulation-Sequencing bitmap palette.

Once you have instantiated the test benches and Sequencer controller, your top-level design will look something like:

You are now ready to set the sequence, edit the Sequencer parameters and add each test bench in the desired order. When you first bring up the edit parameter box, you'll see the available test benches in the left pane.

Add each test bench by either clicking >>Add>> or double-clicking the desired test bench in the order you wish to run the test benches. This will move the selected test bench from the available list to the sequence list in the right pane. To reorder the sequence, use Raise and Lower located below the right pane.

Now your setup is complete and you can run the simulation.

Notes

1. The top-level design should not contain any components other than test benches. Any connectivity (wires) are ignored. Any subnetwork in the top-level design that has one or more pins is ignored.
2. Only one Sequencer controller is allowed.
3. In addition to the Sequencer controller you can use auxiliary simulation controllers: Options Plan, Sweep Plan, Parameter Sweep, Optimization, Statistical, and DOE controllers.
4. Variable equations (simulator expressions) and measurement expressions are supported. As with any top-level design, variables defined at the top are recognized throughout the hierarchy.
5. Tuning is supported.
6. Global nodes are supported, but they are not global across test benches. They are global within each test bench.
7. Any global expression found in a test bench is available to all other test benches.

Examples

For reference, a simple Ptolemy sequencer example is included in ADS.
See /examples/Tutorial/Sequencer_prj documentation for more details.
Additionally, BER connected solutions examples are also available on Microsoft Windows.
See the following examples documentation located in the ADS Examples Documentation:

• 3GPP Uplink BER Receiver Characteristics Test
• WLAN 802.11a Receiver Input Level Sensitivity Test
• Simple Ptolemy Sequencer

Usage Rules

1. DSP cosimulation with A/RF is not supported.
2. Test benches cannot refer to data saved in a dataset from a previous test bench. You can work around this limitation on the DSP schematic. See the simple example above for more details.
3. A test bench cannot contain a Sequencer or S-parameter test lab controller.

Using Measurement Equations with a Test Lab or Sequencer

In either S-parameter Test Lab or Sequencer simulations, measurement equations are used in the same manner as they are in a standard analysis. However, because of the hierarchy associated with an S-parameter configuration, you need to specify the test bench instance ID when a measurement equation at the top-level refers to data generated for a test bench. The format is,

MeasEqnName = TestBenchInstanceID.Sij

where i=1,2,... and j=1,2,... are port indices.

The examples below illustrate this concept:

Example 1: Expressing S11 from test benches X1 and X2

S11_testbenchX1 = X1.S11

S11_testbenchX2 = X2.S11

Example 2: Utilizing S21 from test benches TB1 and TB2

S21_add = TB1.S21 + TB2.S21

S21_divide = TB1.S21/TB2.S21

Example 3: Taking stability function for test benches TB1 and TB2

Stabfact_TB1=stab_fact(TB1.S)

Stabfact_TB2=stab_fact(TB2.S)

Improving Test Lab Simulation Efficiency

Significant time performance gains in test lab simulation can be achieved by minimizing the number of different test benches in the ADS test lab. Using the same test bench repeatedly can result in faster test lab simulation. To take advantage of this, you must have a situation requiring different versions of the same circuit.

To set up a test lab for improved simulation efficiency:

1. In the test circuit, place variables on the component parameters that define the different states.
2. In the test circuit, create passed parameters using the variables created in step 1. Passed parameters are created by choosing File > Design Parameters and selecting the Parameter Tab .
3. Create a test bench containing the test circuit you created previously.
4. In the test bench, create a set of passed parameters. Create one passed parameter in the test bench for each passed parameter created in the test circuit.
5. Create a test lab. Make multiple placements of the test bench. With each placement, assign the passed parameters such that each passed parameter set defines the state of each circuit to be tested.

Doing this, you are effectively placing the same test bench multiple times and each placement defines a different circuit state by the passed parameters used.