Digital Predistortion Using Test Equipment
Digital predistortion linearizes the non-linear response of a power amplifier over an operating region. It uses digital signal processing techniques to condition a baseband signal prior to modulation, up-conversion, and amplification by the power amplifier.
Digital Predistortion within Advanced Design System uses a series of system simulations and system sub-networks developed and implemented to evaluate the performance of digital predistortion. The implemented designs contain sufficient flexibility such that a variety of system sub-networks and a large number of system parameters can be readily changed so that the impact of those changes on system performance can be evaluated. The system simulations and sub-networks include the ability to interface the digital predistortion algorithm with an electronic signal generator (ESG) and a vector signal analyzer (VSA) so that the performance of the digital predistortion system can be evaluated using an actual amplifier. The following illustration summarizes the design flow for digital predistortion within ADS.
This process typically requires two iterations. You may need to perform the simulations until the desired digital predistortion improvement is obtained. After three iterations, sufficient linearization is usually obtained. Once the look-up table coefficients are finalized, adjust ESG power to obtained the desired output power and perform final measurements.
Step 1: Open the DesignGuide
The Digital Predistortion DesignGuide provides step-by-step instructions and templates to create the predistorted versions of the desired modulation. To use the this DesignGuide, open a schematic window and choose DesignGuide > Linearization > Digital Predistortion
Several of the signal sources provided in the DesignGuide require ADS Design Libraries. The cdma2000 sources require the cdma2000 Design Library, and the WCDMA sources require the 3GPP (3rd Generation Partnership Project) Design Library. The source used for the Digital Predistortion Demonstration is derived from a saved dataset, and does not require a Design Library. The source used in the test bench Test_PARofModSig_OQPSK also does not require a Design Library.
Step 2: Initialize Look Up Table Coefficients
Specify the number of entries desired in the Look-up table of coefficients.
Choose DesignGuide > Linearization > Digital Predistortion (Ptolemy/ESG-VSA) > Digital Predistortion Using ESG-VSA > Step 1. Initialize LUT Coefficients to display a dialog box pre-loaded with the filename LUT_initfile_256. This file supports a Look-up table with a size of 256 entries; this size is recommended for most applications.
Click OK to display another dialog box where you can enter the number of Look-up table entries desired. A default value of 256 is entered. Click OK to reset the number of look-up entries to 1 + j x 0.0.
For digital predistortion using ESG-VSA, begin with Step 3: Run ESG Simulation to first copy the Look-up table data files and ESG simulation template to your local project. Once this is done, continue with Step 2: Initialize Look Up Table Coefficients.
Step 3: Run ESG Simulation
Copy the ESG simulation template to your project.
Choose DesignGuide > Linearization > Digital Predistortion (Ptolemy/ESG-VSA) > Digital Predistortion Using ESG-VSA > Step 2. Run ESG Simulation and Download Signal to display the ESG simulation design and data display, which has two pages, Main and LUT signals. Save these files to your project directory. The Main data display page contains the Power_Difference_dB may function. This value will later be entered into the VAR expression ESGIndParameters for ESGAmplitude. The test frequency, ESGCarrierFrequency, should also be set at this time, in units of Hz. Running the ESG Simulation will set the ESG output power, download the signal, trigger the VSA, and enable the RF output of the ESG. Refer to the ESG_E4438C_Sink for more information on setting the interface parameters.
Step 4: Run VSA Simulation
Copy the VSA simulation template to your project.
Choose DesignGuide > Linearization > Digital Predistortion (Ptolemy/ESG-VSA) > Digital Predistortion Using ESG-VSA > Step 3. Run ESG Simulation and Record Response to display the VSA simulation design and data display. When you save these files to your project directory, the VSA setup file is also copied to your project's /data directory.
Start the VSA manually with the VSA setup file selected using File > Recall > Recall Setup.
Modify the center frequency using MeasSetup > Frequency as required, then re-save the file. Close the VSA window at this time; it will be re-opened when the simulation is run. Selecting this menu item will also open the associated display window, which has five pages.
When the VSA simulation is run, certain data from the ESG simulation is directly passed to the VSA simulation. In addition, the VSA Source downloads the DUT's output signal. At this point, the VSA may be manually set to run mode and the time domain waveform examined. The peak value of the ramp (Vpeak) will be dependent upon the gain of the DUT, because the ESG signal is normalized to a magnitude of 1. Due to this gain, the value of VSAScaleFactor in the VSAIndParameters VAR component should be set to 1/Vpeak. For example, if Vpeak is 3.07V, set VSAScaleFactor to 1/3.07 or 0.326. This value will not need to be changed for subsequent simulations.
Once VSAScaleFactor has been set, run the VSA simulation again to obtain the first iteration of LUT coefficients.
Use time averaging to improve the dynamic range performance of the VSA. The included setup file enables averaging, as follows:
- Averaged measurements are not handled as a special case by the VSA_89600_Source component
- Each 89600 analyzer trace update is output to the simulation
The default 89600 analyzer average setup has "Fast Average" disabled, so the traces are updated each time new measurement results are added to the average, starting with the first measurement.
To force only the final, fully averaged result to be output to the simulation, choose MeasSetup > Average on the 89600 analyzer and check both the "Fast Average" and the "Same as Count" options. This will prevent the analyzer from updating the screen until the selected number of measurements have been averaged together.
Step 5: Update Coefficients
Update the number of entries desired in the Look-up table of coefficients.
Choose DesignGuide > Linearization > Digital Predistortion (Ptolemy/ESG-VSA) > Digital Predistortion Using ESG-VSA > Step 4. Update LUT Coefficients to display a dialog box pre-loaded with the filename LUT_datafile_256.txt. This file will be processed to obtain the I and Q files in the correct format for use by the look-up table.
Step 6: Re-Run ESG Simulation
Re-run the ESG simulation, which will now use the look-up table coefficients obtained during the first iteration of Digital Predistortion. When the data display is shown, note the value of Power_Difference_dB on the Main page.
Add the value of Power_Difference_dB into the VAR expression ESGIndParameters for ESGAmplitude such that ESGAmplitude is adjusted by the value of Power_Difference_dB. It is necessary to compensate for gain expansion or compression due to the look-up table by offsetting the ESG output power by this amount. Run the ESG simulation again to drive the DUT at the corrected power level. Repeat this for each set of look-up table coefficients.