3GPPFDD RF Downlink

SpecVersion

version of specifications: Version_03_00, Version_12_00, Version_03_02

Version_12_00

enum

ROut

output resistance

DefaultROut

Ohm

real

(0, ∞)

FCarrier

carrier frequency

2140e6

Hz

real

(0, ∞)

Power

RF output power

0.01

W

real

[0, ∞)

PhasePolarity

if set to Invert, Q channel signal is inverted: DL_Normal, DL_Invert

DL_Normal

enum

GainImbalance

gain imbalance, I to Q channel, in dB

0.0

real

(∞, ∞)

PhaseImbalance

phase imbalance, I to Q channel, in degrees

0.0

real

(∞, ∞)

I_OriginOffset

I origin offset in percent with respect to output rms voltage

0.0

real

(∞, ∞)

Q_OriginOffset

Q origin offset in percent with respect to output rms voltage

0.0

real

(∞, ∞)

IQ_Rotation

IQ rotation in degress

0.0

real

(∞, ∞)

NDensity

additive noise density in dBm per Hz

-10000

real

(∞, ∞)

SamplesPerChip

samples per chip

8

int

[2:32]

ExcessBW

excess bandwidth of raised cosine filters

0.22

real

(0.0:1.0)

FilterLength

length of raised cosine filters in number of symbols

16

int

[2:128]

SourceType

signal source type: Ref_12_2, Ref_64, Ref_144, Ref_384, TestModel1_16DPCHs, TestModel1_32DPCHs, TestModel1_64DPCHs, TestModel2, TestModel3_16DPCHs, TestModel3_32DPCHs, TestModel4, TestModel5_6DPCHs, TestModel5_14DPCHs, TestModel5_30DPCHs

Ref_12_2

enum

ScrambleCode

index of scramble code

0

int

[0:511]

ScrambleOffset

scramble offset in downlink channels

0

int

[0:15]

ScrambleType

scramble type: Normal, RightAlternate, LeftAlternate

Normal

enum

DPCH_SpreadCode

spread code index of DPCH

127

int

[0:DPCH Spread Factor -1 ]

CPICH_SpreadCode

spread code index of CPICH

2

int

[0:255]

PICH_SpreadCode

spread code index of PICH

16

int

[0:255]

SCCPCH_SlotFormat

SCCPCH slot format

0

int

[0:17]

SCCPCH_SpreadCode

spread code index of SCCPCH

3

int

[0:SCCPCH Spread Factor -1 ]

DPCH_GainFactor

DPCH power gain in dB

0

dB

real

(∞, ∞)

P_CPICH_GainFactor

primary CPICH power gain in dB

7

dB

real

(∞, ∞)

S_CPICH_GainFactor

secondary CPICH power gain in dB

-300

dB

real

(∞, ∞)

PCCPCH_GainFactor

PCCPCH power gain in dB

5

dB

real

(∞, ∞)

SCCPCH_GainFactor

SCCPCH power gain in dB

-300

dB

real

(∞, ∞)

P_SCH_GainFactor

primary SCH power gain in dB

2

dB

real

(∞, ∞)

S_SCH_GainFactor

secondary SCH power gain in dB

2

dB

real

(∞, ∞)

PICH_GainFactor

PICH power gain in dB

2

dB

real

(∞, ∞)

OCNS_ChannelNum

OCNS channel number

1

int

[1:512]

OCNS_PowerArray

OCNS channel power array in dB

-300

dB

real array

(∞, ∞)
array size shall be equal to OCNS_ChannelNum

OCNS_SpreadFactorArray

orthogonal channel spread factor array

128

int array

2ⁿ, n=2,...,9
array size shall be equal to OCNS_ChannelNum

OCNS_SpreadCodeArray

orthogonal channel spread code array

2

int array

[0, SpreadFactor-1];
array size shall be equal to OCNS_ChannelNum

OCNS_DataPatternArray

OCNS data pattern array: 0-random, 1-PN9, 2-PN15, 3-Repeat Bits

0

int array

[0,1,2,3];
array size shall be equal to OCNS_ChannelNum

OCNS_RepBitValueArray

OCNS repeat bit value array

0

int array

[0, 255];
array size shall be equal to OCNS_ChannelNum

OCNS_tOffsetArray

time offset of each channel in terms of 256 chips

0

int array

[0, 149];
array size shall be equal to OCNS_ChannelNum

TM_OutputMode

output mode of test model: Ramp, Stable

Ramp

enum

SCCPCH_SltFmt

SCCPCH slot format: SF0, SF1, SF2, SF3

SF0

enum

TM4_EnableP_CPICH

Test Model 4 enable primary CPICH?: NO, YES

YES

enum

TM4_PCCPCH_SCH_Gain

Test Model 4 PCCPCH_SCH level setting

-6

dB

real

(∞, ∞)

TM4_P_CPICH_Gain

Test Model 4 P_CPICH level setting

-6

dB

real

(∞, ∞)

1

RFout

output RF signal

timed

2

EVMRef

reference signal for EVM

complex

3

DTCH

DTCH data

int

4

DCCH

DCCH data

int

5

DPCH

DPCH data

real