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3GPPFDD_DnLinkRF



Description: 3GPP FDD downlink signal source
Library: 3GPPFDD, Base Station
Class: TSDF3GPPFDD_DnLinkRF
Derived From: baseARFsource

Parameters

Name

Description

Default

Symbol

Unit

Type

Range

ROut

Source resistance

DefaultROut

 

Ohm

real

(0, ∞)

RTemp

Temperature

DefaultRTemp

 

Celsius

real

[-273.15, ∞)

TStep

Expression showing how TStep is related to the other source parameters

1/3.84 MHz/SamplesPerChip

 

 

string

 

FCarrier

Carrier frequency

2140 MHz

 

Hz

real

(0, ∞)

Power

Power

dbmtow(43.0)

 

W

real

[0, ∞)

MirrorSpectrum

Mirror spectrum about carrier?: NO, YES

NO

 

 

enum

 

GainImbalance

Gain imbalance, Q vs I

0.0

 

dB

real

(∞, ∞)

PhaseImbalance

Phase imbalance, Q vs I

0.0

 

deg

real

(∞, ∞)

I_OriginOffset

I origin offset (percent)

0.0

 

 

real

(∞, ∞)

Q_OriginOffset

Q origin offset (percent)

0.0

 

 

real

(∞, ∞)

IQ_Rotation

IQ rotation

0.0

 

deg

real

(∞, ∞)

SamplesPerChip

Samples per chip

8

S

 

int

[2:32]

RRC_FilterLength

RRC filter length (chips)

16

 

 

int

[2:128]

SpecVersion

Specification version: Version 03_00, Version 12_00, Version 03_02

Version 12_00

 

 

enum

 

SourceType

Source type: TestModel1_16DPCHs, TestModel1_32DPCHs, TestModel1_64DPCHs, TestModel2, TestModel3_16DPCHs, TestModel3_32DPCHs, TestModel4

TestModel1_16DPCHs

 

 

enum

 

Pin Outputs

Pin

Name

Description

Signal Type

1

RF

RF output

timed

2

I

I symbols

real

3

Q

Q symbols

real

Notes/Equations
  1. This 3GPP FDD signal source generates a downlink RF signal of 3GPP FDD test models. The RF signal has a chip rate of 3.84 MHz. The downlink is from the base station to the user equipment.
    To use this source RF carrier frequency (FCarrier) and power (Power) must be set.
    RF impairments can be introduced by setting the ROut, RTemp, MirrorSpectrum, GainImbalance, PhaseImbalance, I_OriginOffset, Q_OriginOffset, and IQ_Rotation parameters.
    3GPP FDD signal characteristics can be specified by setting the RRC_FilterLength, SpecVersion, and SourceType parameters.

    Note

    While the function of this model is similar to 3GPPFDD_RF_Downlink, some parameter and output pins are different.

  2. This signal source includes a DSP section, RF modulator, and RF output resistance as illustrated in the following figure.

    Signal Source Block Diagram
    The ROut and RTemp parameters are used by the RF output resistance. The FCarrier, Power, MirrorSpectrum, GainImbalance, PhaseImbalance, I_OriginOffset, Q_OriginOffset, and IQ_Rotation parameters are used by the RF modulator. The remaining signal source parameters are used by the DSP block.
    The RF output from the signal source is at the frequency specified (FCarrier), with the specified source resistance (ROut) and with power (Power) delivered into a matched load of resistance ROut. The RF signal has additive Gaussian noise power set by the resistor temperature (RTemp).
    The I and Q outputs are baseband outputs with zero source resistance and contain the unfiltered I and Q chips available at the RF modulator input. Because the I and Q outputs are from the inputs to the RF modulator, the RF output signal has a time delay relative to the I and Q chips. This RF time delay (RF_Delay) is related to the RRC_FilterLength parameter value.

    RF_Delay = RRC_FilterLength/(3.84e6)/2 sec

  3. This 3GPP FDD signal source model is compatible with Agilent E4438C ESG Vector Signal Generator, Option 400 (3GPP W-CDMA Firmware Option for the E4438C ESG Vector Signal Generator).
    Details regarding Agilent E4438C ESG for 3GPP FDD are included at the website http://www.keysight.com/find/signalstudio.
  4. Regarding the 3GPP downlink signal frame structure, one frame has a time duration of 10 msec and consists of 15 slots. Each slot contains 2560 chips. Each chip is an RF signal symbol.
    There is only one type of downlink dedicated physical channel, the downlink dedicated physical channel (downlink DPCH).
    Within one downlink DPCH, dedicated data generated at Layer 2 and above, i.e. the dedicated transport channel (DCH), is transmitted in time-multiplex with control information generated at Layer 1. The Layer 1 control information consists of known pilot bits to support channel estimation for coherent detection, transmit power-control (TPC) commands, and an optional transport-format combination indicator (TFCI). The TFCI informs the receiver about the instantaneous transport format combination of the transport channels mapped to the simultaneously transmitted downlink DPCH radio frame.
    The downlink DPCH can therefore be seen as a time multiplex of a downlink DPDCH (Data1 and Data2) and a downlink DPCCH (TPC, TFCI, and Pilot).
    The frame and slot structure of the downlink DPCH is illustrated in the following figure. The last 2 tables provide more information about each field.

    3GPP FDD Downlink Frame and Slot Structure
  5. Parameter Details
    • ROut is the RF output source resistance.
    • RTemp is the RF output source resistance temperature in Celsius and sets the noise density in the RF output signal to (k(RTemp + 273.15)) Watts/Hz, where k is Boltzmann's constant.
    • FCarrier is the RF output signal frequency.
    • Power is the RF output signal power delivered into a matched load of resistance ROut.
    • MirrorSpectrum is used to mirror the RF_out signal spectrum about the carrier. This is equivalent to conjugating the complex RF envelope voltage.
      Depending on the configuration and number of mixers in an RF transmitter, the RF output signal from hardware RF generators can be inverted. If such an RF signal is desired, set this parameter to YES.
    • GainImbalance, PhaseImbalance, I_OriginOffset, Q_OriginOffset, and IQ_Rotation are used to add certain impairments to the ideal output RF signal. Impairments are added in the order described here.
      The unimpaired RF I and Q envelope voltages have gain and phase imbalance applied. The RF is given by:

      where A is a scaling factor based on the Power and ROut parameters specified by the designer, V I( t ) is the in-phase RF envelope, V Q( t ) is the quadrature phase RF envelope, g is the gain imbalance

      and, φ (in degrees) is the phase imbalance.
      Next, the signal VRF( t ) is rotated by IQ_Rotation degrees. I_OriginOffset and Q_OriginOffset are then applied to the rotated signal. Note that the amounts specified are percentages with respect to the output rms voltage. The output rms voltage is given by sqrt(2 × ROut × Power).
    • SamplesPerChip is used to set the number of samples in a chip.
      The default value is set to 8 to display settings according to the 3GPP standard. It can be set to a larger value for a simulation frequency bandwidth wider than 8 × 3.84 MHz. It can be set to a smaller value for faster simulation; however, this will result in lower signal fidelity. If SamplesPerChip = 8, the simulation RF bandwidth is larger than the signal bandwidth by a factor of 8 (e.g., simulation RF bandwidth = 8 × 3.84 MHz).
    • RRC_FilterLength is used to set root raised-cosine (RRC) filter length in number of chips.
      The default value is set to 16 to transmit a 3GPP FDD downlink signal in time and frequency domains based on the 3GPP standard defined in [4]. It can be set to a smaller value for faster simulation times; however, this will result in lower signal fidelity.
    • SpecVersion is used to specify the 3GPP specification versions (2000-03, 2000-12 and 2002-03).
    • SourceType is used to specify the type of baseband signal that can be generated by this source based on the test model as defined in [5].
      TestModel1_16DPCHs, TestModel1_32DPCHs, TestModel1_64DPCHs. The following table lists the active channels of Test Model 1 that tests spectrum emission mask, ACLR, spurious emissions, transmit intermodulation, and base station maximum output power.
      Test Model 1 Active Channels
      Type Number of Channels Fraction of Power (%) Level Setting (dB) Channelization Code Timing Offset (x256Tchip)
      PCCPCH+SCH 1 10 -10 1 0
      Primary CPICH 1 10 -10 0 0
      PICH 1 1.6 -18 16 120
      SCCPCH containing PCH (SF=256) 1 1.6 -18 3 0
      DPCH (SF=128) †† 16/32/64 76.8 total see [5] see [5] see [5]
      †SCCPCH containing PCH is not included in versions 2000-03 and 2000-12 [5].
      †† Refer to the "DPCH Structure for Test Model 1 and Test Model 2" table below for DPCH structure.
      TestModel2. The following table lists the active channels in Test Model 2 that tests output power dynamics.
      Test Model 2 Active Channels
      Type Number of Channels Fraction of Power (%) Level Setting (dB) Channelization Code Timing Offset (x256Tchip)
      PCCPCH+SCH 1 10 -10 1 0
      Primary CPICH 1 10 -10 0 0
      PICH 1 5 -13 16 120
      S-CCPCH containing PCH (SF=256) 1 5 -13 3 0
      DPCH (SF=128) †† 3 2 x 10,1 x 50 2 x -10, 1 x -3 24, 72, 120 1, 7, 2
      †SCCPCH containing PCH is not included in versions 2000-03 and 2000-12 [5].
      †† Refer to the "DPCH Structure for Test Model 1 and Test Model 2" table below for DPCH structure.
      TestModel3_16DPCHs, TestModel3_32DPCHs. The following table lists the active channels of Test Model 3 that tests peak code domain error.
      Test Model 3 Active Channels
      Type Number of Channels Fraction of Power (%) 16/32 Level Settings (dB) 16/32 Channelization Code Timing Offset (x256Tchip)
      PCCPCH+SCH 1 12.6/7.9 -9 / -11 1 0
      Primary CPICH 1 12.6/7.9 -9 / -11 0 0
      PICH 1 5/1.6 -13 / -18 16 120
      SCCPCH containing PCH (SF=256) † 1 5/1.6 -13 / -18 3 0
      DPCH (SF=256) †† 16/32 63,7/80,4 total see Reference [5] see Reference [5] see Reference [5]
      †SCCPCH containing PCH is not included in versions 2000-03 and 2000-12 [5]
      †† Refer to the "DPCH Structure for Test Model 3" table below for DPCH structure.
      TestModel4. The following table lists the active channels of Test Model 4 that tests EVM.
      Test Model 4 Active Channels
      Type Number of Channels Fraction of Power (%) 16/32 Level Settings (dB) 16/32 Channelization Code Timing Offset (x256Tchip)
      PCCPCH+SCH when Primary CPICH is disabled 1 50 to 1.6 -3 to -18 1 0
      PCCPCH+SCH when Primary CPICH is enabled 1 25 to 0.8 -6 to -21 1 0
      Primary CPICH† 1 25 to 0.8 -6 to -21 0 0
      † Primary CPICH is optional; it is not included in versions 2000-03 and 2000-12 [5]
      DPCH Structure for Test Model 1 and Test Model 2
      Slot Format No. Channel Bit Rate (kbps) Channel Symbol Rate (kbps) SF Bits / Slot DPDCH Bits / Slot DPCCH Bits / Slot
      NData1 NData2 NTFCI NTPC Npilot
      10 60 30 128 40 6 24 0 2 8
      DPCH Structure for Test Model 3
      Slot Format No. Channel Bit Rate (kbps) Channel Symbol Rate (kbps) SF Bits / Slot DPDCH Bits / Slot DPCCH Bits / Slot
      NData1 NData2 NTFCI NTPC Npilot
      6 30 15 256 20 2 8 0 2 8

References
  1. 3GPP Technical Specification TS 25.211, "Physical channels and mapping of transport channels onto physical channels (FDD)" Release 1999.

    http://www.3gpp.org/ftp/Specs/2002-03/R1999/25_series/25211-3a0.zip

  2. 3GPP Technical Specification TS 25.212, "Multiplexing and Channel Coding (FDD)" Release 1999.

    http://www.3gpp.org/ftp/Specs/2002-03/R1999/25_series/25212-390.zip

  3. 3GPP Technical Specification TS 25.213, "Spreading and modulation (FDD)" Release 1999.

    http://www.3gpp.org/ftp/Specs/2002-03/R1999/25_series/25213-370.zip

  4. 3GPP Technical Specification TS 25.104, "UTRA (BS) FDD; Radio transmission and Reception" Release 1999.

    http://www.3gpp.org/ftp/Specs/2002-03/R1999/25_series/25104-3a0.zip

  5. 3GPP Technical Specification TS 25.141, "Base station conformance testing (FDD)" Release 1999.

    http://www.3gpp.org/ftp/Specs/2002-03/R1999/25_series/25141-390.zip

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