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3GPPFDD_CodeDomainErr



Description: 3GPP FDD code domain error measurement
Library: 3GPPFDD, Measurement
Class: SDF3GPPFDD_CodeDomainErr
Derived From: 3GPPFDD_MeasBase

Parameters

Name

Description

Default

Unit

Type

Range

SpecVersion

version of specifications: Version_03_00, Version_12_00, Version_03_02

Version_12_00

 

enum

 

LinkDir

link direction: Downlink, Uplink

Uplink

 

enum

 

SlotFormat

slot format

0

 

int

ScrambleCode

index of scramble code

0

 

int

[0:512] for downlink;
[0, 16777215] for uplink

Scramble

scramble code type: LONG, SHORT

LONG

 

enum

 

ScrambleOffset

scramble code offset

0

 

int

[0:15]

ScrambleType

scramble code type: normal, right, left

normal

 

enum

 

SpreadCode

index of spread code

0

 

int

[0:SF-1];
SF can be set by SlotFormat or equal to SpreadFactor;
SF is 256 if for CPICH, PICH or uplink DPCCH

SampleRate

sample rate

8

 

int

[1:256]

MaxDelaySample

maximum delay boundary, in terms of samples

0

 

int

[0:2559] for RAKE receiver;
[0:102400] in other models

StartSlot

number of slot to be ignored

0

 

int

[0, ∞)

SymBurstLen

burst length in term of symbol

2560

 

int

[16, 5120]

Correlator

correlator method: Coherent, NonCoherent

Coherent

 

enum

 

SCH

switch for SCH: SCH_On, SCH_Off

SCH_On

 

enum

 

CPICH

switch for CPICH: CPICH_On, CPICH_Off

CPICH_Off

 

enum

 

Correct_IQ_Offset

switch for IQ offset correction: Yes, No

Yes

 

enum

 

RefSlotBoundary

reference signal slot boundary in terms of sample

0

 

int

[0:102400/Interp];
Interp=int(128/SampleRate)

TestSlotBoundary

test signal slot boundary in terms of sample

0

 

int

[0:102400/Interp];
Interp=int(128/SampleRate)

CodeLayer

the code layer to calculate the peak code error

8

 

int

[2:9]

† [0:5] for uplink DPCCH;

[0:16] for downlink DPCH;

[0:17] for downlink SCCPCH;

[0:5] for uplink PCPCH (Ver 03_00);

[0:2] for uplink PCPCH (Ver 12_00);

[0:1] for uplink PCPCH (Ver 03_02);

Uplink DPCCH spread factor is 256;

Spread Factor is 512 when down link DPCH SlotFormat is 0 and 1;

Spread Factor is 256 when down link DPCH SlotFormat is 2, 3, 4, 5, 6, and 7;

Spread Factor is 128 when down link DPCH SlotFormat is 8, 9, 10, and 11;

Spread Factor is 64 when down link DPCH SlotFormat is 12;

Spread Factor is 32 when down link DPCH SlotFormat is 13;

Spread Factor is 16 when down link DPCH SlotFormat is 14;

Spread Factor is 8 when down link DPCH SlotFormat is 15;

Spread Factor is 4 when down link DPCH SlotFormat is 16;

Pin Inputs

Pin

Name

Description

Signal Type

1

test

tested signals

complex

2

ref

reference signals

complex

Notes/Equations
  1. This subnetwork model is used to measure 3GPP code domain error. The schematic for this subnetwork is shown in the following figure.

    3GPPFDD_CodeDomainErr Schematic
  2. The test and reference signals are interpolated to ensure that each chip has 128 samples. A 6-order Lagrange interpolation is used; the interpolation rate is determined by the symbol sample rate. For more information regarding the synchronization process refer to 3GPPFDD_Synch.
  3. After synchronization, the measurement sequence is down-sampled to chip rate. The code domain error is measured at the chip times within one burst.
  4. CodeLayer specifies the code layer on which the code domain error is measured.
    Code domain error is the error vector projection over each OVSF code on the specified layer. Error vector is defined as the difference between the reference and the test signal. The test signal is compensated by phase shift and frequency and phase error. Compensation of IQ origin offset on the test signal is optional.
  5. Correct_IQ_Offset indicates if the original IQ offset is to be included in the code domain error calculation.
  6. The algorithm used to measure code domain error is defined in Annex B.2.7.2 of [2] in which Code domain error is not clearly stated to be normalized against spread factor (SF); this can lead to a difference of 10 × log10(SF) dB if the code domain error is normalized against SF. In this subnetwork model, code domain error is normalized against spread factor (SF).
  7. RefSlotBoundary and TestSlotBoundary are used to set the slot boundary for the reference and test signals, respectively. If the value is set to 0, the slot boundary is determined by the synchronization model; otherwise, the non-zero value is taken as the slot boundary. Please note this boundary is for the interpolated slot that has a higher sample rate.
  8. If the test signal is severely impaired, the slot boundary may not be correctly determined by the internal synchronization model. In these cases, the source where the impairment is introduced must first be manually removed. The slot boundary reported in the simulation panel measured under ideal conditions can then be written back to the parameter set to specify the correct slot boundary.

References
  1. 3GPP Technical Specification TS 25.211 V3.10.0, Physical channels and mapping of transport channels onto physical channels (FDD), March 2003, Release 1999.

    http://www.3gpp.org/ftp/Specs/2002-03/R1999/25_series/25211-3a0.zip

  2. 3GPP Technical Specification TS 34.121 V3.8.0, Terminal Conformance Specification, Radio Transmission and Reception (FDD), March 2003, Release 1999.

    http://www.3gpp.org/ftp/Specs/2002-03/R1999/34_series/34121-380.zip

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